From 1aa6d0a16d6fce99c5f4df2f709a0d9154d20d9d Mon Sep 17 00:00:00 2001
From: mwojcik <mw@m-labs.hk>
Date: Mon, 16 Jan 2023 18:13:55 +0800
Subject: [PATCH] test_dma: remove tsc mode

---
 src/gateware/test_dma.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gateware/test_dma.py b/src/gateware/test_dma.py
index c0786a3..456205f 100644
--- a/src/gateware/test_dma.py
+++ b/src/gateware/test_dma.py
@@ -168,7 +168,7 @@ class FullStackTB(Module):
         bus = axi.Interface(ws*8)
         self.memory = AXIMemorySim(bus, sequence)
         self.submodules.dut = dma.DMA(bus)
-        self.submodules.tsc = rtio.TSC("async")
+        self.submodules.tsc = rtio.TSC()
         self.submodules.rtio = rtio.Core(self.tsc, rtio_channels)
         self.comb += self.dut.cri.connect(self.rtio.cri)