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helloworld_ecp5: add delays between messages

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Otherwise the FTDI UART goes out of sync and corrupts data.
This commit is contained in:
Sebastien Bourdeauducq 2019-04-30 15:52:38 +08:00
parent 1cf460b56f
commit d84b172245
1 changed files with 11 additions and 2 deletions
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13
examples/helloworld_ecp5.py
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@ -22,17 +22,26 @@ class Top(Elaboratable):
init=[ord(c) for c in string]) init=[ord(c) for c in string])
m.submodules.rdport = rdport = mem.read_port(synchronous=False) m.submodules.rdport = rdport = mem.read_port(synchronous=False)
wait = Signal()
tx = uart.RS232TX(round(2**32*self.baudrate/100e6)) tx = uart.RS232TX(round(2**32*self.baudrate/100e6))
m.submodules.tx = tx m.submodules.tx = tx
m.d.comb += [ m.d.comb += [
tx.stb.eq(1), tx.stb.eq(~wait),
tx.data.eq(rdport.data), tx.data.eq(rdport.data),
self.serial_tx.eq(tx.tx) self.serial_tx.eq(tx.tx)
] ]
with m.If(tx.ack): release = Signal()
counter = Signal(25)
m.d.sync += Cat(counter, release).eq(counter + 1)
with m.If(release):
m.d.sync += wait.eq(0)
with m.If(~wait & tx.ack):
with m.If(rdport.addr == len(string) - 1): with m.If(rdport.addr == len(string) - 1):
m.d.sync += rdport.addr.eq(0) m.d.sync += rdport.addr.eq(0)
m.d.sync += wait.eq(1)
with m.Else(): with m.Else():
m.d.sync += rdport.addr.eq(rdport.addr + 1) m.d.sync += rdport.addr.eq(rdport.addr + 1)