From d84b17224515b7f49dbeae4980e93763cb055281 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 30 Apr 2019 15:52:38 +0800 Subject: [PATCH] helloworld_ecp5: add delays between messages Otherwise the FTDI UART goes out of sync and corrupts data. --- examples/helloworld_ecp5.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/examples/helloworld_ecp5.py b/examples/helloworld_ecp5.py index a209094..a9cce8d 100644 --- a/examples/helloworld_ecp5.py +++ b/examples/helloworld_ecp5.py @@ -22,17 +22,26 @@ class Top(Elaboratable): init=[ord(c) for c in string]) m.submodules.rdport = rdport = mem.read_port(synchronous=False) + wait = Signal() + tx = uart.RS232TX(round(2**32*self.baudrate/100e6)) m.submodules.tx = tx m.d.comb += [ - tx.stb.eq(1), + tx.stb.eq(~wait), tx.data.eq(rdport.data), self.serial_tx.eq(tx.tx) ] - with m.If(tx.ack): + release = Signal() + counter = Signal(25) + m.d.sync += Cat(counter, release).eq(counter + 1) + with m.If(release): + m.d.sync += wait.eq(0) + + with m.If(~wait & tx.ack): with m.If(rdport.addr == len(string) - 1): m.d.sync += rdport.addr.eq(0) + m.d.sync += wait.eq(1) with m.Else(): m.d.sync += rdport.addr.eq(rdport.addr + 1)