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simplesoc_ecp5: run simulation longer

This commit is contained in:
Sebastien Bourdeauducq 2019-06-08 23:00:57 +08:00
parent c7bda2b144
commit 328a521632
1 changed files with 1 additions and 1 deletions
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2
examples/simplesoc_ecp5.py
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@ -85,7 +85,7 @@ def main():
vcd_file=open(args.output_file + ".vcd", "w"),
gtkw_file=open(args.output_file + ".gtkw", "w")) as sim:
sim.add_clock(1e-6)
sim.run_until(100e-6, run_passive=True)
sim.run_until(1000e-6, run_passive=True)
else:
output = rtlil.convert(Fragment.get(top, None),
ports=(top.clk100, top.led, top.serial_tx))