diff --git a/examples/simplesoc_ecp5.py b/examples/simplesoc_ecp5.py
index a92a377..1a1e674 100644
--- a/examples/simplesoc_ecp5.py
+++ b/examples/simplesoc_ecp5.py
@@ -85,7 +85,7 @@ def main():
                 vcd_file=open(args.output_file + ".vcd", "w"),
                 gtkw_file=open(args.output_file + ".gtkw", "w")) as sim:
             sim.add_clock(1e-6)
-            sim.run_until(100e-6, run_passive=True)
+            sim.run_until(1000e-6, run_passive=True)
     else:
         output = rtlil.convert(Fragment.get(top, None),
             ports=(top.clk100, top.led, top.serial_tx))