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468 Commits

Author SHA1 Message Date
David Mak fc93fc2f0e core: Move bitcode verification error message into panic message 2023-09-22 17:16:29 +08:00
David Mak dd42022633 core: Minor refactor allocate_list 2023-09-22 17:16:29 +08:00
David Mak 6dfc43c8b0 core: Add name to build_gep_and_load 2023-09-22 17:16:29 +08:00
David Mak ab2360d7a0 core: Remove emit_llvm from CodeGenLLVMOptions 
We instead output an LLVM bitcode file when the option is specified on
the command-line.
 2023-09-22 17:16:29 +08:00
David Mak ee1ee4ab3b core: Replace deprecated _ExtInt with _BitInt 2023-09-22 17:16:29 +08:00
David Mak 3e430b9b40 core: Fix missing changes for codegen tests 
Apparently the changes were dropped after rebasing.
 2023-09-22 17:16:21 +08:00
David Mak 048fcb0a69 core: Switch to LLVM New Pass Manager 2023-09-18 11:35:15 +08:00
David Mak 676d07657a core: Add target field to CodeGenLLVMOptions 
For specifying the target machine options when optimizing and linking.

This field is currently unused but will be required in a future
commit.
 2023-09-18 09:46:24 +08:00
David Mak 2482a1ef9b core: Add CodeGenTargetMachineOptions 
Needed in a future commit.
 2023-09-18 09:41:49 +08:00
David Mak eb63f2ad48 meta: Update to Rust Edition 2021 2023-09-15 10:25:50 +08:00
David Mak 3993a5cf3f core: Add LLVM options to WorkerRegistry 2023-09-12 10:57:05 +08:00
David Mak 39724de598 core: Add CodeGenLLVMOptions 
For specifying LLVM options during code generation.
 2023-09-12 10:57:04 +08:00
David Mak 4481d48709 core: Use C-style for loop logic for iterables 
Index increment is now performed at the end of the loop body.
 2023-09-06 20:09:38 +08:00
David Mak b4983526bd core: Remove redundant for.cond BB for iterable loops 
Simplifies logic for creating basic blocks.
 2023-09-06 20:09:37 +08:00
David Mak b4a9616648 core: Add assertion for when `range` has step of 0 
Aligns with the behavior in Python.
 2023-09-06 20:09:36 +08:00
David Mak e0de82993f core: Preserve value of variable shadowed by for loop 
Previously, the final value of the target expression would be one after
the last element of the loop, which does not match Python's behavior.

This commit fixes this problem while also preserving the last assigned
value of the loop beyond the loop, matching Python's behavior.
 2023-09-06 20:09:36 +08:00
David Mak 6805253515 core: Use AST var name for IR name 
Aids debugging IR.
 2023-09-06 20:09:36 +08:00
David Mak 19915bac79 core: Prepend statement type to basic block label names 
Aids debugging IR.
 2023-09-06 20:09:36 +08:00
David Mak 6de0884dc1 core: Use anonymous name for variables if unspecified 
The current default prefix is only derived from the instruction type,
which is not helpful during the comprehension of the IR. Changing to
anonymous names (e.g. %1) helps understand that the variable is only
needed as part of a larger (possibly named) expression.
 2023-09-06 14:02:15 +08:00
David Mak f1b0e05b3d core: Rename IR variables 
Because it is unclear which variables are expressions and
subexpressions, all variables which are previously anonymous are named
using (1) the control flow statement if available, (2) the possible name
of the variable as inferred from the variable name in Rust, and (3) the
"addr" prefix to indicate that the values are pointers. These three
strings are joint together using '.', forming "for.i.addr" for instance.
 2023-09-06 14:02:15 +08:00
David Mak ff23968544 core: Add name parameter to gen_{var_alloc,store_target} 
This allows variables in the IR to be assigned a custom name as opposed
to names with a default prefix.
 2023-09-06 11:00:02 +08:00
David Mak d37287a33d Cargo: Update dependencies 2023-09-04 10:43:57 +08:00
Sebastien Bourdeauducq aead36f0fd update dependencies 2023-03-08 15:19:09 +08:00
Sebastien Bourdeauducq c1c45373a6 update dependencies 2023-01-12 19:31:03 +08:00
Sebastien Bourdeauducq 085c6ee738 update dependencies 2022-11-18 16:15:46 +08:00
Sebastien Bourdeauducq f66ca02b2d update Rust dependencies 2022-08-05 16:58:57 +08:00
z78078 ebd25af38b nac3standalone: allow classes without explicit init (#221) 
Reviewed-on: M-Labs/nac3#304
Co-authored-by: z78078 <cc@m-labs.hk>
Co-committed-by: z78078 <cc@m-labs.hk>
 2022-07-07 10:36:25 +08:00
z78078 96b3a3bf5c work around random segmentation fault (#275) 
Reviewed-on: M-Labs/nac3#302
Co-authored-by: z78078 <cc@m-labs.hk>
Co-committed-by: z78078 <cc@m-labs.hk>
 2022-07-04 18:06:36 +08:00
ychenfo a18d095245 nac3core: codegen fix call parameter type error 2022-07-04 14:39:33 +08:00
ychenfo 5d5e9a5e02 nac3core: fix codegen error of inheritance 2022-06-01 17:58:16 +08:00
ychenfo c4ab2855e5 nac3core: pretty print codegen panic error 2022-05-30 04:09:21 +08:00
ychenfo ffac37dc48 nac3core: fix exception type in primitive store 2022-05-29 19:14:00 +08:00
ychenfo 76473152e8 nac3core: fix llvm.expect intrinsic name 
this might be one of the causes for the random segfault bug
 2022-05-27 04:23:49 +08:00
ychenfo 096f4b03c0 nac3core: fix assignment 2022-05-14 02:30:08 +08:00
ychenfo a022005183 nac3core: fix broken tests 2022-05-11 03:53:53 +08:00
ychenfo 325ba0a408 nac3core: add debug info 2022-05-11 03:53:53 +08:00
Sebastien Bourdeauducq 3f327113b2 update dependencies, use upstream inkwell 2022-04-27 15:41:46 +08:00
Sebastien Bourdeauducq a321b13bec fix typos 2022-04-27 11:08:10 +08:00
ychenfo 48cb485b89 nac3core: show outer type info in type error messages 
Reviewed-on: M-Labs/nac3#274
Co-authored-by: ychenfo <yc@m-labs.hk>
Co-committed-by: ychenfo <yc@m-labs.hk>
 2022-04-22 15:31:55 +08:00
Sebastien Bourdeauducq 85f21060e4 update to LLVM 14 2022-04-18 18:47:20 +08:00
Sebastien Bourdeauducq 1eac111d4c cleanup 2022-04-18 15:55:37 +08:00
ychenfo 711c3d3303 nac3core: support custom operators 2022-04-18 15:31:56 +08:00
wylited 35b6459c58 nac3core: replace paramter with parameter 2022-04-13 15:42:26 +08:00
wylited e94b25f544 spelling (#264) 
Co-authored-by: wylited <ds@m-labs.hk>
Co-committed-by: wylited <ds@m-labs.hk>
 2022-04-13 11:32:31 +08:00
Sebastien Bourdeauducq 1e7abf0268 fix tests 2022-04-12 10:06:41 +08:00
Sebastien Bourdeauducq f5a6d29106 update insta snapshots 2022-04-12 09:56:49 +08:00
Sebastien Bourdeauducq ca07cb66cd format typevars consistently 2022-04-12 09:28:17 +08:00
ychenfo 722e3df086 nac3core, artiq: optimize kernel invariant for tuple index 2022-04-11 14:58:40 +08:00
ychenfo ad9ad22cb8 nac3core: optimize unwrap KernelInvariant 2022-04-11 14:58:35 +08:00
ychenfo f66f66b3a4 nac3core, artiq: remove unnecessary ptr casts 2022-04-10 01:28:46 +08:00