stevefan1999/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Issues Pull Requests Projects Releases Wiki Activity

gateware: replaced wb slave w/ axi (diff soccore)

Browse Source
This commit is contained in:
mwojcik 2021-08-06 11:05:49 +02:00
parent f9860a61b7
commit d68cf7dd49
2 changed files with 5 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/gateware/kasli_soc.py
View File

@ -272,9 +272,7 @@ class GenericMaster(SoCCore):
self.csr_devices.append(coreaux_name) self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800, self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtio", drtio_csr_group)
@ -422,9 +420,7 @@ class GenericSatellite(SoCCore):
self.csr_devices.append(coreaux_name) self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800, self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group)

8
src/gateware/zc706.py
View File

@ -316,9 +316,7 @@ class Master(ZC706):
self.csr_devices.append(coreaux_name) self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800, self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtio", drtio_csr_group)
@ -428,9 +426,7 @@ class Satellite(ZC706):
self.csr_devices.append(coreaux_name) self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800, self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group)