forked from M-Labs/artiq-zynq
satman: init gateware, set log level
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7d719d07e9
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@ -18,7 +18,7 @@ extern crate unwind;
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extern crate alloc;
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extern crate alloc;
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use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio};
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use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio, slcr};
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use libsupport_zynq::ram;
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use libsupport_zynq::ram;
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#[cfg(has_si5324)]
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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use libboard_artiq::si5324;
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@ -33,6 +33,29 @@ use libregister::{RegisterW, RegisterR};
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mod repeater;
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mod repeater;
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fn init_gateware() {
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// Set up PS->PL clocks
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slcr::RegisterBlock::unlocked(|slcr| {
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// As we are touching the mux, the clock may glitch, so reset the PL.
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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.fpga0_out_rst(true)
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.fpga1_out_rst(true)
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.fpga2_out_rst(true)
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.fpga3_out_rst(true)
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);
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slcr.fpga0_clk_ctrl.write(
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slcr::Fpga0ClkCtrl::zeroed()
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.src_sel(slcr::PllSource::IoPll)
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.divisor0(8)
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.divisor1(1)
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);
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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);
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});
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}
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fn drtiosat_reset(reset: bool) {
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fn drtiosat_reset(reset: bool) {
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unsafe {
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unsafe {
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csr::drtiosat::reset_write(if reset { 1 } else { 0 });
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csr::drtiosat::reset_write(if reset { 1 } else { 0 });
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@ -447,8 +470,10 @@ pub extern fn main_core0() -> i32 {
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};
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};
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buffer_logger.set_uart_log_level(log::LevelFilter::Info);
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buffer_logger.set_uart_log_level(log::LevelFilter::Info);
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buffer_logger.register();
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buffer_logger.register();
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log::set_max_level(log::LevelFilter::Info);
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//probably will have to copy init_gateware() from runtime here too
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//probably will have to copy init_gateware() from runtime here too
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init_gateware();
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info!("ARTIQ satellite manager starting...");
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info!("ARTIQ satellite manager starting...");
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info!("gateware ident {}", identifier_read(&mut [0; 64]));
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info!("gateware ident {}", identifier_read(&mut [0; 64]));
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