diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs
index 7967411b..de66829b 100644
--- a/src/satman/src/main.rs
+++ b/src/satman/src/main.rs
@@ -18,7 +18,7 @@ extern crate unwind;
 
 extern crate alloc;
 
-use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio};
+use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio, slcr};
 use libsupport_zynq::ram;
 #[cfg(has_si5324)]
 use libboard_artiq::si5324;
@@ -33,6 +33,29 @@ use libregister::{RegisterW, RegisterR};
 
 mod repeater;
 
+fn init_gateware() {
+    // Set up PS->PL clocks
+    slcr::RegisterBlock::unlocked(|slcr| {
+        // As we are touching the mux, the clock may glitch, so reset the PL.
+        slcr.fpga_rst_ctrl.write(
+            slcr::FpgaRstCtrl::zeroed()
+                .fpga0_out_rst(true)
+                .fpga1_out_rst(true)
+                .fpga2_out_rst(true)
+                .fpga3_out_rst(true)
+        );
+        slcr.fpga0_clk_ctrl.write(
+            slcr::Fpga0ClkCtrl::zeroed()
+                .src_sel(slcr::PllSource::IoPll)
+                .divisor0(8)
+                .divisor1(1)
+        );
+        slcr.fpga_rst_ctrl.write(
+            slcr::FpgaRstCtrl::zeroed()
+        );
+    });
+}
+
 fn drtiosat_reset(reset: bool) {
     unsafe {
         csr::drtiosat::reset_write(if reset { 1 } else { 0 });
@@ -447,8 +470,10 @@ pub extern fn main_core0() -> i32 {
     };
     buffer_logger.set_uart_log_level(log::LevelFilter::Info);
     buffer_logger.register();
+    log::set_max_level(log::LevelFilter::Info);
     
     //probably will have to copy init_gateware() from runtime here too
+    init_gateware();
 
     info!("ARTIQ satellite manager starting...");
     info!("gateware ident {}", identifier_read(&mut [0; 64]));