forked from M-Labs/zynq-rs
172 lines
4.8 KiB
Rust
172 lines
4.8 KiB
Rust
use core::ops::Deref;
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use alloc::{vec, vec::Vec};
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use libcortex_a9::{asm::*, cache::*, UncachedSlice};
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use libregister::*;
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use super::Buffer;
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#[derive(Debug)]
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pub enum Error {
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HrespNotOk,
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RxOverrun,
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BufferNotAvail,
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Truncated,
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}
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/// Descriptor entry
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#[repr(C, align(0x08))]
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pub struct DescEntry {
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word0: DescWord0,
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word1: DescWord1,
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}
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impl DescEntry {
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pub fn zeroed() -> Self {
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DescEntry {
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word0: DescWord0 { inner: VolatileCell::new(0) },
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word1: DescWord1 { inner: VolatileCell::new(0) },
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}
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}
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}
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register!(desc_word0, DescWord0, VolatileCell, u32);
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register_bit!(desc_word0,
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/// true if owned by software, false if owned by hardware
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used, 0);
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register_bit!(desc_word0,
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/// mark last desc in list
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wrap, 1);
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register_bits!(desc_word0, address, u32, 2, 31);
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register!(desc_word1, DescWord1, VolatileCell, u32);
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register_bits!(desc_word1, frame_length_lsbs, u16, 0, 12);
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register_bit!(desc_word1, bad_fcs, 13);
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register_bit!(desc_word1, start_of_frame, 14);
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register_bit!(desc_word1, end_of_frame, 15);
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register_bit!(desc_word1, cfi, 16);
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register_bits!(desc_word1, vlan_priority, u8, 17, 19);
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register_bit!(desc_word1, priority_tag, 20);
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register_bit!(desc_word1, vlan_tag, 21);
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register_bits!(desc_word1, bits_22_23, u8, 22, 23);
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register_bit!(desc_word1, bit_24, 24);
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register_bits!(desc_word1, spec_addr_which, u8, 25, 26);
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register_bit!(desc_word1, spec_addr_match, 27);
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register_bit!(desc_word1, uni_hash_match, 29);
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register_bit!(desc_word1, multi_hash_match, 30);
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register_bit!(desc_word1, global_broadcast, 31);
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#[repr(C)]
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pub struct DescList {
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list: UncachedSlice<DescEntry>,
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buffers: Vec<Buffer>,
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next: usize,
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}
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impl DescList {
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pub fn new(size: usize) -> Self {
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let mut list = UncachedSlice::new(size, || DescEntry::zeroed())
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.unwrap();
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let mut buffers = vec![Buffer::new(); size];
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let last = list.len().min(buffers.len()) - 1;
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for (i, (entry, buffer)) in list.iter_mut().zip(buffers.iter_mut()).enumerate() {
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let is_last = i == last;
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let buffer_addr = &mut buffer.0[0] as *mut _ as u32;
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assert!(buffer_addr & 0b11 == 0);
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entry.word0.write(
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DescWord0::zeroed()
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.used(false)
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.wrap(is_last)
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.address(buffer_addr >> 2)
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);
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entry.word1.write(
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DescWord1::zeroed()
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);
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// Flush buffer from cache, to be filled by the peripheral
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// before next read
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dcci_slice(&buffer[..]);
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}
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DescList {
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list,
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buffers,
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next: 0,
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}
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}
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pub fn len(&self) -> usize {
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self.list.len().min(self.buffers.len())
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}
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pub fn list_addr(&self) -> u32 {
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&self.list[0] as *const _ as u32
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}
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pub fn recv_next<'s: 'p, 'p>(&'s mut self) -> Result<Option<PktRef<'p>>, Error> {
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let list_len = self.list.len();
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let entry = &mut self.list[self.next];
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dmb();
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if entry.word0.read().used() {
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let word1 = entry.word1.read();
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let len = word1.frame_length_lsbs().into();
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let padding = {
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let diff = len % 0x20;
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if diff == 0 {
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0
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} else {
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0x20 - diff
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}
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};
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unsafe {
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// invalidate the buffer
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// we cannot do it in the drop function, as L2 cache data prefetch would prefetch
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// the data, and there is no way for us to prevent that unless changing MMU table.
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dci_slice(&mut self.buffers[self.next][0..len + padding]);
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}
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let buffer = &mut self.buffers[self.next][0..len];
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self.next += 1;
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if self.next >= list_len {
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self.next = 0;
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}
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let pkt = PktRef { entry, buffer };
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if word1.start_of_frame() && word1.end_of_frame() {
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Ok(Some(pkt))
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} else {
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Err(Error::Truncated)
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}
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} else {
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Ok(None)
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}
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}
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}
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/// Releases a buffer back to the HW upon Drop
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pub struct PktRef<'a> {
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entry: &'a mut DescEntry,
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buffer: &'a mut [u8],
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}
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impl<'a> Drop for PktRef<'a> {
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fn drop(&mut self) {
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self.entry.word0.modify(|_, w| w.used(false));
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dmb();
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}
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}
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impl<'a> Deref for PktRef<'a> {
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type Target = [u8];
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fn deref(&self) -> &Self::Target {
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self.buffer
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}
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}
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impl<'a> smoltcp::phy::RxToken for PktRef<'a> {
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fn consume<R, F>(self, _timestamp: smoltcp::time::Instant, f: F) -> smoltcp::Result<R>
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where
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F: FnOnce(&mut [u8]) -> smoltcp::Result<R>
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{
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f(self.buffer)
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}
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}
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