forked from M-Labs/zynq-rs
Compare commits
22 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
| 213529cf7a | |||
| 4cfcc75d5c | |||
| 578431cbc6 | |||
| 6188fe7d69 | |||
| 2713b459ed | |||
| 0ea7e2c760 | |||
| fa660a7433 | |||
| d2ec041107 | |||
| 48ab85bf2e | |||
| d477272c5c | |||
| 80180ba8f6 | |||
| 12975de2e1 | |||
| 8c404829ef | |||
| 8f041b017c | |||
| 5815baf88b | |||
| cc20478d91 | |||
| 5ef3016554 | |||
| 6a45a0dfd0 | |||
| b2b3e5c933 | |||
| 0efbbe39fe | |||
| 51b8111e79 | |||
| 46dc25b89e |
38
Cargo.lock
generated
38
Cargo.lock
generated
@ -1,5 +1,7 @@
|
||||
# This file is automatically @generated by Cargo.
|
||||
# It is not intended for manual editing.
|
||||
version = 3
|
||||
|
||||
[[package]]
|
||||
name = "bit_field"
|
||||
version = "0.10.1"
|
||||
@ -14,9 +16,9 @@ checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
|
||||
|
||||
[[package]]
|
||||
name = "byteorder"
|
||||
version = "1.4.3"
|
||||
version = "1.3.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
|
||||
checksum = "60f0b0d4c0a382d2734228fd12b5a6b5dac185c60e938026fd31b265b94f9bd2"
|
||||
|
||||
[[package]]
|
||||
name = "cc"
|
||||
@ -32,18 +34,14 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
|
||||
|
||||
[[package]]
|
||||
name = "compiler_builtins"
|
||||
version = "0.1.39"
|
||||
version = "0.1.49"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
|
||||
checksum = "20b1438ef42c655665a8ab2c1c6d605a305f031d38d9be689ddfef41a20f3aa2"
|
||||
|
||||
[[package]]
|
||||
name = "core_io"
|
||||
version = "0.1.20210325"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "97f8932064288cc79feb4d343a399d353a6f6f001e586ece47fe518a9e8507df"
|
||||
dependencies = [
|
||||
"rustc_version",
|
||||
]
|
||||
version = "0.1.0"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/rs-core_io.git?rev=e9d3edf027#e9d3edf0272502b0dd6c26e8a4869c2912657615"
|
||||
|
||||
[[package]]
|
||||
name = "embedded-hal"
|
||||
@ -70,9 +68,8 @@ dependencies = [
|
||||
|
||||
[[package]]
|
||||
name = "fatfs"
|
||||
version = "0.3.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "e18f80a87439240dac45d927fd8f8081b6f1e34c03e97271189fa8a8c2e96c8f"
|
||||
version = "0.3.6"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/rust-fatfs.git?rev=4b5e420084#4b5e420084fd1c4a9c105680b687523909b6469c"
|
||||
dependencies = [
|
||||
"bitflags",
|
||||
"byteorder",
|
||||
@ -196,21 +193,6 @@ version = "1.0.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "bd7a31eed1591dcbc95d92ad7161908e72f4677f8fabf2a32ca49b4237cbf211"
|
||||
|
||||
[[package]]
|
||||
name = "rustc_version"
|
||||
version = "0.1.7"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "c5f5376ea5e30ce23c03eb77cbe4962b988deead10910c372b226388b594c084"
|
||||
dependencies = [
|
||||
"semver",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "semver"
|
||||
version = "0.1.20"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
|
||||
|
||||
[[package]]
|
||||
name = "smoltcp"
|
||||
version = "0.7.5"
|
||||
|
||||
@ -1,12 +1,4 @@
|
||||
{
|
||||
"abi-blacklist": [
|
||||
"stdcall",
|
||||
"fastcall",
|
||||
"vectorcall",
|
||||
"thiscall",
|
||||
"win64",
|
||||
"sysv64"
|
||||
],
|
||||
"arch": "arm",
|
||||
"data-layout": "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64",
|
||||
"emit-debug-gdb-scripts": false,
|
||||
|
||||
@ -8,6 +8,7 @@ edition = "2018"
|
||||
[features]
|
||||
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
|
||||
target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
|
||||
target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205"]
|
||||
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
|
||||
target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"]
|
||||
default = ["target_zc706"]
|
||||
|
||||
@ -1,12 +1,14 @@
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(const_in_array_repeat_expressions)]
|
||||
#![allow(incomplete_features)]
|
||||
#![feature(naked_functions)]
|
||||
#![feature(asm)]
|
||||
#![feature(inline_const)]
|
||||
|
||||
extern crate alloc;
|
||||
|
||||
use alloc::collections::BTreeMap;
|
||||
use core::arch::asm;
|
||||
use libasync::{
|
||||
delay,
|
||||
smoltcp::{Sockets, TcpStream},
|
||||
@ -116,6 +118,7 @@ pub fn main_core0() {
|
||||
|
||||
#[cfg(any(
|
||||
feature = "target_zc706",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
|
||||
49
flake.lock
generated
49
flake.lock
generated
@ -1,41 +1,46 @@
|
||||
{
|
||||
"nodes": {
|
||||
"mozilla-overlay": {
|
||||
"flake": false,
|
||||
"locked": {
|
||||
"lastModified": 1704373101,
|
||||
"narHash": "sha256-+gi59LRWRQmwROrmE1E2b3mtocwueCQqZ60CwLG+gbg=",
|
||||
"owner": "mozilla",
|
||||
"repo": "nixpkgs-mozilla",
|
||||
"rev": "9b11a87c0cc54e308fa83aac5b4ee1816d5418a2",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
"owner": "mozilla",
|
||||
"repo": "nixpkgs-mozilla",
|
||||
"type": "github"
|
||||
}
|
||||
},
|
||||
"nixpkgs": {
|
||||
"locked": {
|
||||
"lastModified": 1715087517,
|
||||
"narHash": "sha256-CLU5Tsg24Ke4+7sH8azHWXKd0CFd4mhLWfhYgUiDBpQ=",
|
||||
"lastModified": 1734529975,
|
||||
"narHash": "sha256-ze3IJksru9dN0keqUxY0WNf8xrwfs8Ty/z9v/keyBbg=",
|
||||
"owner": "NixOS",
|
||||
"repo": "nixpkgs",
|
||||
"rev": "b211b392b8486ee79df6cdfb1157ad2133427a29",
|
||||
"rev": "72d11d40b9878a67c38f003c240c2d2e1811e72a",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
"owner": "NixOS",
|
||||
"ref": "nixos-unstable",
|
||||
"ref": "nixos-24.05",
|
||||
"repo": "nixpkgs",
|
||||
"type": "github"
|
||||
}
|
||||
},
|
||||
"root": {
|
||||
"inputs": {
|
||||
"mozilla-overlay": "mozilla-overlay",
|
||||
"nixpkgs": "nixpkgs"
|
||||
"nixpkgs": "nixpkgs",
|
||||
"rust-overlay": "rust-overlay"
|
||||
}
|
||||
},
|
||||
"rust-overlay": {
|
||||
"inputs": {
|
||||
"nixpkgs": [
|
||||
"nixpkgs"
|
||||
]
|
||||
},
|
||||
"locked": {
|
||||
"lastModified": 1719454714,
|
||||
"narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
|
||||
"owner": "oxalica",
|
||||
"repo": "rust-overlay",
|
||||
"rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
"owner": "oxalica",
|
||||
"ref": "snapshot/2024-08-01",
|
||||
"repo": "rust-overlay",
|
||||
"type": "github"
|
||||
}
|
||||
}
|
||||
},
|
||||
|
||||
49
flake.nix
49
flake.nix
@ -1,30 +1,29 @@
|
||||
{
|
||||
description = "Bare-metal Rust on Zynq-7000";
|
||||
|
||||
inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-unstable;
|
||||
inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; };
|
||||
inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.05;
|
||||
inputs.rust-overlay = {
|
||||
url = "github:oxalica/rust-overlay?ref=snapshot/2024-08-01";
|
||||
inputs.nixpkgs.follows = "nixpkgs";
|
||||
};
|
||||
|
||||
outputs = { self, nixpkgs, mozilla-overlay }:
|
||||
outputs = { self, nixpkgs, rust-overlay }:
|
||||
let
|
||||
pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) crosspkgs-overlay ]; };
|
||||
pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import rust-overlay) crosspkgs-overlay ]; };
|
||||
|
||||
rustManifest = pkgs.fetchurl {
|
||||
url = "https://static.rust-lang.org/dist/2021-01-29/channel-rust-nightly.toml";
|
||||
sha256 = "sha256-EZKgw89AH4vxaJpUHmIMzMW/80wAFQlfcxRoBD9nz0c=";
|
||||
rust = pkgs.rust-bin.nightly."2021-09-01".default.override {
|
||||
extensions = [ "rust-src" ];
|
||||
targets = [ ];
|
||||
};
|
||||
rustTargets = [];
|
||||
rustChannelOfTargets = _channel: _date: targets:
|
||||
(pkgs.lib.rustLib.fromManifestFile rustManifest {
|
||||
inherit (pkgs) stdenv lib fetchurl patchelf;
|
||||
}).rust.override {
|
||||
inherit targets;
|
||||
extensions = ["rust-src"];
|
||||
rustPlatform = pkgs.makeRustPlatform {
|
||||
rustc = rust // {
|
||||
# https://github.com/oxalica/rust-overlay/commit/c48c2d76b68dd9ede0815fec53479375c61af857
|
||||
targetPlatforms = pkgs.lib.platforms.all;
|
||||
tier1TargetPlatforms = pkgs.lib.platforms.all;
|
||||
badTargetPlatforms = [ ];
|
||||
};
|
||||
rust = rustChannelOfTargets "nightly" null rustTargets;
|
||||
rustPlatform = pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
|
||||
rustc = rust;
|
||||
cargo = rust;
|
||||
});
|
||||
};
|
||||
|
||||
crosspkgs-overlay = (self: super: {
|
||||
pkgsCross = super.pkgsCross // {
|
||||
@ -106,9 +105,15 @@
|
||||
src = builtins.filterSource (path: type:
|
||||
baseNameOf path != "target"
|
||||
) ./.;
|
||||
cargoLock = { lockFile = ./Cargo.lock; };
|
||||
cargoLock = {
|
||||
lockFile = ./Cargo.lock;
|
||||
outputHashes = {
|
||||
"core_io-0.1.0" = "sha256-0HINFWRiJx8pjMgUOL/CS336ih7SENSRh3Kah9LPRrw=";
|
||||
"fatfs-0.3.6" = "sha256-Nz9hCq/1YgSXF8ltJ5ZawV0Hc8WV44KNK0tJdVnNb4U=";
|
||||
};
|
||||
};
|
||||
|
||||
nativeBuildInputs = [ cargo-xbuild pkgs.llvmPackages_14.clang-unwrapped ];
|
||||
nativeBuildInputs = [ cargo-xbuild pkgs.llvmPackages_13.clang-unwrapped ];
|
||||
buildPhase = ''
|
||||
export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
|
||||
export CARGO_HOME=$(mktemp -d cargo-home.XXX)
|
||||
@ -134,7 +139,7 @@
|
||||
"${target}-experiments" = build-crate "${target}-experiments" "experiments" "target_${target}";
|
||||
"${target}-szl" = build-crate "${target}-szl" "szl" "target_${target}";
|
||||
};
|
||||
targets = ["zc706" "coraz7" "redpitaya" "kasli_soc"];
|
||||
targets = ["zc706" "coraz7" "redpitaya" "kasli_soc" "ebaz4205"];
|
||||
allTargetCrates = (builtins.foldl' (results: target:
|
||||
results // targetCrates target
|
||||
) {} targets);
|
||||
@ -164,7 +169,7 @@
|
||||
|
||||
pkgs.openocd pkgs.gdb
|
||||
pkgs.openssh pkgs.rsync
|
||||
pkgs.llvmPackages_14.clang-unwrapped
|
||||
pkgs.llvmPackages_13.clang-unwrapped
|
||||
(pkgs.python3.withPackages(ps: [ ps.pyftdi ]))
|
||||
];
|
||||
};
|
||||
|
||||
@ -8,6 +8,7 @@ edition = "2018"
|
||||
[features]
|
||||
target_zc706 = []
|
||||
target_coraz7 = []
|
||||
target_ebaz4205 = []
|
||||
target_redpitaya = []
|
||||
target_kasli_soc = []
|
||||
ipv6 = [ "smoltcp/proto-ipv6" ]
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
use core::unimplemented;
|
||||
|
||||
use libregister::{RegisterR, RegisterRW};
|
||||
use super::slcr;
|
||||
pub use slcr::ArmPllSource;
|
||||
@ -101,6 +103,8 @@ impl Clocks {
|
||||
self.ddr,
|
||||
slcr::PllSource::IoPll =>
|
||||
self.io,
|
||||
slcr::PllSource::Emio =>
|
||||
unimplemented!(),
|
||||
};
|
||||
pll / u32::from(uart_clk_ctrl.divisor())
|
||||
}
|
||||
@ -115,6 +119,8 @@ impl Clocks {
|
||||
self.ddr,
|
||||
slcr::PllSource::IoPll =>
|
||||
self.io,
|
||||
slcr::PllSource::Emio =>
|
||||
unimplemented!(),
|
||||
};
|
||||
pll / u32::from(sdio_clk_ctrl.divisor())
|
||||
}
|
||||
|
||||
@ -6,6 +6,8 @@ use super::slcr;
|
||||
pub const PS_CLK: u32 = 33_333_333;
|
||||
#[cfg(feature = "target_coraz7")]
|
||||
pub const PS_CLK: u32 = 50_000_000;
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
pub const PS_CLK: u32 = 33_333_333;
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
pub const PS_CLK: u32 = 33_333_333;
|
||||
#[cfg(feature = "target_kasli_soc")]
|
||||
|
||||
@ -16,6 +16,10 @@ const DDR_FREQ: u32 = 666_666_666;
|
||||
/// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
|
||||
const DDR_FREQ: u32 = 525_000_000;
|
||||
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
/// EtronTech Memory EM6GD16EWKG-12H: 800 MHz DDR3 at 533 MHz
|
||||
const DDR_FREQ: u32 = 533_333_333;
|
||||
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
|
||||
const DDR_FREQ: u32 = 533_333_333;
|
||||
@ -147,22 +151,23 @@ impl DdrRam {
|
||||
.output_en(slcr::DdriobOutputEn::Obuf);
|
||||
#[cfg(feature = "target_zc706")]
|
||||
let data1_config = data0_config.clone();
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
let data0_config = slcr::DdriobConfig::zeroed()
|
||||
.inp_type(slcr::DdriobInputType::VrefDifferential)
|
||||
.term_en(true)
|
||||
.dci_type(slcr::DdriobDciType::Termination)
|
||||
.output_en(slcr::DdriobOutputEn::Obuf);
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
|
||||
let data1_config = slcr::DdriobConfig::zeroed()
|
||||
.pullup_en(true);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
let data0_config = slcr::DdriobConfig::zeroed()
|
||||
.inp_type(slcr::DdriobInputType::VrefDifferential)
|
||||
.term_en(true)
|
||||
.dci_type(slcr::DdriobDciType::Termination)
|
||||
.output_en(slcr::DdriobOutputEn::Obuf);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
let data1_config = slcr::DdriobConfig::zeroed()
|
||||
.pullup_en(true);
|
||||
slcr.ddriob_data0.write(data0_config);
|
||||
@ -176,22 +181,23 @@ impl DdrRam {
|
||||
.output_en(slcr::DdriobOutputEn::Obuf);
|
||||
#[cfg(feature = "target_zc706")]
|
||||
let diff1_config = diff0_config.clone();
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
let diff0_config = slcr::DdriobConfig::zeroed()
|
||||
.inp_type(slcr::DdriobInputType::Differential)
|
||||
.term_en(true)
|
||||
.dci_type(slcr::DdriobDciType::Termination)
|
||||
.output_en(slcr::DdriobOutputEn::Obuf);
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
|
||||
let diff1_config = slcr::DdriobConfig::zeroed()
|
||||
.pullup_en(true);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
let diff0_config = slcr::DdriobConfig::zeroed()
|
||||
.inp_type(slcr::DdriobInputType::Differential)
|
||||
.term_en(true)
|
||||
.dci_type(slcr::DdriobDciType::Termination)
|
||||
.output_en(slcr::DdriobOutputEn::Obuf);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
let diff1_config = slcr::DdriobConfig::zeroed()
|
||||
.pullup_en(true);
|
||||
slcr.ddriob_diff0.write(diff0_config);
|
||||
@ -210,7 +216,12 @@ impl DdrRam {
|
||||
slcr.ddriob_drive_slew_clock.write(0x00F9861C);
|
||||
}
|
||||
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
slcr.ddriob_ddr_ctrl.modify(|_, w| w
|
||||
.vref_int_en(false)
|
||||
.vref_ext_en_lower(true)
|
||||
@ -224,13 +235,6 @@ impl DdrRam {
|
||||
.vref_ext_en_lower(false)
|
||||
.vref_ext_en_upper(false)
|
||||
);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
slcr.ddriob_ddr_ctrl.modify(|_, w| w
|
||||
.vref_int_en(false)
|
||||
.vref_ext_en_lower(true)
|
||||
.vref_ext_en_upper(false)
|
||||
.refio_en(true)
|
||||
);
|
||||
});
|
||||
}
|
||||
|
||||
@ -242,6 +246,13 @@ impl DdrRam {
|
||||
.t_rfc_min(0x9e)
|
||||
.post_selfref_gap_x32(0x10)
|
||||
);
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
self.regs.dram_param0.write(
|
||||
regs::DramParam0::zeroed()
|
||||
.t_rc(0x1a)
|
||||
.t_rfc_min(0x56)
|
||||
.post_selfref_gap_x32(0x10)
|
||||
);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
self.regs.dram_param0.write(
|
||||
regs::DramParam0::zeroed()
|
||||
@ -256,6 +267,12 @@ impl DdrRam {
|
||||
.t_rfc_min(0x56)
|
||||
.post_selfref_gap_x32(0x10)
|
||||
);
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
self.regs.dram_param1.modify(
|
||||
|_, w| w
|
||||
.t_faw(0x16)
|
||||
.t_ras_min(0x13)
|
||||
);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
self.regs.dram_param1.modify(
|
||||
|_, w| w
|
||||
@ -277,6 +294,11 @@ impl DdrRam {
|
||||
.rd2pre(0x4)
|
||||
.t_rcd(0x7)
|
||||
);
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
self.regs.dram_param3.modify(
|
||||
|_, w| w
|
||||
.t_rp(7)
|
||||
);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
self.regs.dram_param3.modify(
|
||||
|_, w| w
|
||||
@ -298,19 +320,21 @@ impl DdrRam {
|
||||
.emr(0x4)
|
||||
);
|
||||
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
self.regs.phy_configs[2].modify(
|
||||
|_, w| w.data_slice_in_use(false)
|
||||
);
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
|
||||
self.regs.phy_configs[3].modify(
|
||||
|_, w| w.data_slice_in_use(false)
|
||||
);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
self.regs.phy_configs[2].modify(
|
||||
|_, w| w.data_slice_in_use(false)
|
||||
);
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
self.regs.phy_configs[3].modify(
|
||||
|_, w| w.data_slice_in_use(false)
|
||||
);
|
||||
@ -354,7 +378,11 @@ impl DdrRam {
|
||||
.gatelvl_init_ratio(0xee)
|
||||
);
|
||||
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_kasli_soc"),
|
||||
)]
|
||||
self.regs.reg_64.modify(
|
||||
|_, w| w
|
||||
.phy_ctrl_slave_ratio(0x100)
|
||||
@ -390,9 +418,12 @@ impl DdrRam {
|
||||
fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
|
||||
#[cfg(feature = "target_zc706")]
|
||||
let width = regs::DataBusWidth::Width32bit;
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
|
||||
let width = regs::DataBusWidth::Width16bit;
|
||||
#[cfg(feature = "target_redpitaya")]
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
let width = regs::DataBusWidth::Width16bit;
|
||||
self.regs.ddrc_ctrl.modify(|_, w| w
|
||||
.soft_rstb(false)
|
||||
@ -410,6 +441,7 @@ impl DdrRam {
|
||||
}
|
||||
#[cfg(any(
|
||||
feature = "target_coraz7",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_redpitaya",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
@ -450,6 +482,8 @@ impl DdrRam {
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
let megabytes = 512;
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
let megabytes = 256;
|
||||
|
||||
megabytes * 1024 * 1024
|
||||
}
|
||||
|
||||
@ -65,17 +65,31 @@ impl Gem for Gem0 {
|
||||
slcr.gem0_clk_ctrl.write(
|
||||
// 0x0050_0801: 8, 5: 100 Mb/s
|
||||
// ...: 8, 1: 1000 Mb/s
|
||||
#[cfg(not(feature = "target_ebaz4205"))]
|
||||
slcr::GemClkCtrl::zeroed()
|
||||
.clkact(true)
|
||||
.srcsel(slcr::PllSource::IoPll)
|
||||
.divisor(divisor0 as u8)
|
||||
.divisor1(divisor1 as u8),
|
||||
// ebaz4205 -- EMIO
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
slcr::GemClkCtrl::zeroed()
|
||||
.clkact(true)
|
||||
.srcsel(slcr::PllSource::Emio)
|
||||
.divisor(divisor0 as u8)
|
||||
.divisor1(divisor1 as u8)
|
||||
);
|
||||
// Enable gem0 recv clock
|
||||
slcr.gem0_rclk_ctrl.write(
|
||||
// 0x0000_0801
|
||||
#[cfg(not(feature = "target_ebaz4205"))]
|
||||
slcr::RclkCtrl::zeroed()
|
||||
.clkact(true),
|
||||
// ebaz4205 -- EMIO
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
slcr::RclkCtrl::zeroed()
|
||||
.clkact(true)
|
||||
.srcsel(true)
|
||||
);
|
||||
});
|
||||
}
|
||||
@ -154,6 +168,7 @@ pub struct Eth<GEM: Gem, RX, TX> {
|
||||
|
||||
impl Eth<Gem0, (), ()> {
|
||||
pub fn eth0(macaddr: [u8; 6]) -> Self {
|
||||
#[cfg(not(feature = "target_ebaz4205"))]
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
// Manual example: 0x0000_1280
|
||||
// MDIO
|
||||
|
||||
@ -83,6 +83,7 @@ pub struct Phy {
|
||||
const OUI_MARVELL: u32 = 0x005043;
|
||||
const OUI_REALTEK: u32 = 0x000732;
|
||||
const OUI_LANTIQ : u32 = 0x355969;
|
||||
const OUI_ICPLUS : u32 = 0x0090c3;
|
||||
|
||||
//only change pages on Kasli-SoC's Marvel 88E11xx
|
||||
#[cfg(feature="target_kasli_soc")]
|
||||
@ -117,6 +118,12 @@ impl Phy {
|
||||
model: 0,
|
||||
..
|
||||
}) => true,
|
||||
Some(PhyIdentifier {
|
||||
oui: OUI_ICPLUS,
|
||||
// IP101G-DS-R01
|
||||
model: 5,
|
||||
rev: 4,
|
||||
}) => true,
|
||||
_ => false,
|
||||
}
|
||||
}).map(|addr| Phy { addr })
|
||||
|
||||
@ -55,12 +55,22 @@ impl Status {
|
||||
pub fn get_link(&self) -> Option<Link> {
|
||||
if ! self.link_status() {
|
||||
None
|
||||
} else if self.cap_10base_t_half() {
|
||||
} else if self.cap_100base_tx_full() {
|
||||
Some(Link {
|
||||
speed: LinkSpeed::S10,
|
||||
speed: LinkSpeed::S100,
|
||||
duplex: LinkDuplex::Full,
|
||||
})
|
||||
} else if self.cap_100base_tx_half() {
|
||||
Some(Link {
|
||||
speed: LinkSpeed::S100,
|
||||
duplex: LinkDuplex::Half,
|
||||
})
|
||||
} else if self.cap_10base_t_full() {
|
||||
} else if self.cap_100base_t4() {
|
||||
Some(Link {
|
||||
speed: LinkSpeed::S100,
|
||||
duplex: LinkDuplex::Half,
|
||||
})
|
||||
} else if self.cap_10base_t2_full() {
|
||||
Some(Link {
|
||||
speed: LinkSpeed::S10,
|
||||
duplex: LinkDuplex::Full,
|
||||
@ -70,26 +80,16 @@ impl Status {
|
||||
speed: LinkSpeed::S10,
|
||||
duplex: LinkDuplex::Half,
|
||||
})
|
||||
} else if self.cap_10base_t2_full() {
|
||||
} else if self.cap_10base_t_full() {
|
||||
Some(Link {
|
||||
speed: LinkSpeed::S10,
|
||||
duplex: LinkDuplex::Full,
|
||||
})
|
||||
} else if self.cap_100base_t4() {
|
||||
} else if self.cap_10base_t_half() {
|
||||
Some(Link {
|
||||
speed: LinkSpeed::S100,
|
||||
speed: LinkSpeed::S10,
|
||||
duplex: LinkDuplex::Half,
|
||||
})
|
||||
} else if self.cap_100base_tx_half() {
|
||||
Some(Link {
|
||||
speed: LinkSpeed::S100,
|
||||
duplex: LinkDuplex::Half,
|
||||
})
|
||||
} else if self.cap_100base_tx_full() {
|
||||
Some(Link {
|
||||
speed: LinkSpeed::S100,
|
||||
duplex: LinkDuplex::Full,
|
||||
})
|
||||
} else {
|
||||
None
|
||||
}
|
||||
|
||||
@ -4,6 +4,7 @@ use embedded_hal::timer::CountDown;
|
||||
|
||||
pub struct EEPROM<'a> {
|
||||
i2c: &'a mut I2c,
|
||||
#[cfg(not(feature = "target_ebaz4205"))]
|
||||
port: u8,
|
||||
address: u8,
|
||||
page_size: u8,
|
||||
@ -46,6 +47,11 @@ impl<'a> EEPROM<'a> {
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
fn select(&mut self) -> Result<(), &'static str> {
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Random read
|
||||
pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> {
|
||||
self.select()?;
|
||||
|
||||
@ -2,10 +2,13 @@
|
||||
|
||||
mod regs;
|
||||
pub mod eeprom;
|
||||
#[cfg(not(feature = "target_ebaz4205"))]
|
||||
use super::slcr;
|
||||
use super::time::Microseconds;
|
||||
use embedded_hal::timer::CountDown;
|
||||
use libregister::{RegisterR, RegisterRW, RegisterW};
|
||||
use libregister::{RegisterR, RegisterRW};
|
||||
#[cfg(not(feature = "target_ebaz4205"))]
|
||||
use libregister::RegisterW;
|
||||
#[cfg(feature = "target_kasli_soc")]
|
||||
use log::info;
|
||||
|
||||
@ -22,9 +25,10 @@ pub struct I2c {
|
||||
}
|
||||
|
||||
impl I2c {
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
pub fn i2c0() -> Self {
|
||||
// Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
|
||||
#[cfg(not(feature = "target_ebaz4205"))]
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
// SCL
|
||||
slcr.mio_pin_50.write(
|
||||
|
||||
@ -21,6 +21,7 @@ use libregister::{
|
||||
// Current compatibility:
|
||||
// zc706: GPIO 50, 51 == SCL, SDA
|
||||
// kasli_soc: GPIO 50, 51 == SCL, SDA; GPIO 33 == I2C_SW_RESET
|
||||
// ebaz4205: GPIO (EMIO)
|
||||
|
||||
pub struct RegisterBlock {
|
||||
pub gpio_output_mask: &'static mut GPIOOutputMask,
|
||||
@ -48,17 +49,17 @@ register!(gpio_output_mask,
|
||||
/// MASK_DATA_1_MSW:
|
||||
/// Maskable output data for MIO[53:48]
|
||||
GPIOOutputMask, RW, u32);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_at!(GPIOOutputMask, 0xE000A00C, new);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_bit!(gpio_output_mask,
|
||||
/// Output for SCL
|
||||
scl_o, 2);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_bit!(gpio_output_mask,
|
||||
/// Output for SDA
|
||||
sda_o, 3);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_bits!(gpio_output_mask,
|
||||
/// Mask for keeping bits except SCL and SDA unchanged
|
||||
mask, u16, 16, 31);
|
||||
@ -82,13 +83,13 @@ register!(gpio_input,
|
||||
/// DATA_1_RO:
|
||||
/// Input data for MIO[53:32]
|
||||
GPIOInput, RO, u32);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_at!(GPIOInput, 0xE000A064, new);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_bit!(gpio_input,
|
||||
/// Input for SCL
|
||||
scl, 18);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_bit!(gpio_input,
|
||||
/// Input for SDA
|
||||
sda, 19);
|
||||
@ -98,13 +99,13 @@ register!(gpio_direction,
|
||||
/// DIRM_1:
|
||||
/// Direction mode for MIO[53:32]; 0/1 = in/out
|
||||
GPIODirection, RW, u32);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_at!(GPIODirection, 0xE000A244, new);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_bit!(gpio_direction,
|
||||
/// Direction for SCL
|
||||
scl, 18);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_bit!(gpio_direction,
|
||||
/// Direction for SDA
|
||||
sda, 19);
|
||||
@ -117,13 +118,13 @@ register!(gpio_output_enable,
|
||||
/// OEN_1:
|
||||
/// Output enable for MIO[53:32]
|
||||
GPIOOutputEnable, RW, u32);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_at!(GPIOOutputEnable, 0xE000A248, new);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_bit!(gpio_output_enable,
|
||||
/// Output enable for SCL
|
||||
scl, 18);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
register_bit!(gpio_output_enable,
|
||||
/// Output enable for SDA
|
||||
sda, 19);
|
||||
|
||||
@ -19,7 +19,7 @@ pub mod gic;
|
||||
pub mod time;
|
||||
pub mod timer;
|
||||
pub mod sdio;
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
|
||||
pub mod i2c;
|
||||
pub mod logger;
|
||||
pub mod ps7_init;
|
||||
|
||||
@ -116,8 +116,8 @@ impl Sdio {
|
||||
.speed(true),
|
||||
);
|
||||
}
|
||||
// redpitaya card detect pin
|
||||
#[cfg(any(feature = "target_redpitaya", feature = "target_kasli_soc"))]
|
||||
// kasli_soc and redpitaya card detect pin
|
||||
#[cfg(any(feature = "target_kasli_soc", feature = "target_redpitaya"))]
|
||||
{
|
||||
unsafe {
|
||||
slcr.sd0_wp_cd_sel.write(46 << 16);
|
||||
@ -128,6 +128,20 @@ impl Sdio {
|
||||
.speed(true),
|
||||
);
|
||||
}
|
||||
// ebaz4205 card detect pin
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
{
|
||||
unsafe {
|
||||
slcr.sd0_wp_cd_sel.write(34 << 16);
|
||||
}
|
||||
slcr.mio_pin_34.write(
|
||||
slcr::MioPin34::zeroed()
|
||||
.io_type(slcr::IoBufferType::Lvcmos33)
|
||||
.pullup(true)
|
||||
.speed(true),
|
||||
);
|
||||
}
|
||||
|
||||
slcr.sdio_rst_ctrl.reset_sdio0();
|
||||
slcr.aper_clk_ctrl.enable_sdio0();
|
||||
slcr.sdio_clk_ctrl.enable_sdio0();
|
||||
|
||||
@ -9,9 +9,11 @@ use libregister::{
|
||||
|
||||
#[repr(u8)]
|
||||
pub enum PllSource {
|
||||
IoPll = 0b00,
|
||||
ArmPll = 0b10,
|
||||
DdrPll = 0b11,
|
||||
IoPll = 0b000,
|
||||
ArmPll = 0b010,
|
||||
DdrPll = 0b011,
|
||||
// Ethernet controller 0 EMIO clock
|
||||
Emio = 0b100,
|
||||
}
|
||||
|
||||
#[repr(u8)]
|
||||
|
||||
@ -47,7 +47,11 @@ impl DerefMut for LazyUart {
|
||||
LazyUart::Uninitialized => {
|
||||
#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
|
||||
let uart = Uart::uart0(UART_RATE);
|
||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
||||
#[cfg(any(
|
||||
feature = "target_zc706",
|
||||
feature = "target_ebaz4205",
|
||||
feature = "target_kasli_soc",
|
||||
))]
|
||||
let uart = Uart::uart1(UART_RATE);
|
||||
*self = LazyUart::Initialized(uart);
|
||||
self
|
||||
|
||||
@ -79,6 +79,39 @@ impl Uart {
|
||||
self_
|
||||
}
|
||||
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
pub fn uart1(baudrate: u32) -> Self {
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
// Route UART 1 RxD/TxD Signals to MIO Pins
|
||||
// TX pin
|
||||
slcr.mio_pin_24.write(
|
||||
slcr::MioPin24::zeroed()
|
||||
.l3_sel(0b111)
|
||||
.io_type(slcr::IoBufferType::Lvcmos33)
|
||||
.pullup(true)
|
||||
);
|
||||
// RX pin
|
||||
slcr.mio_pin_25.write(
|
||||
slcr::MioPin25::zeroed()
|
||||
.tri_enable(true)
|
||||
.l3_sel(0b111)
|
||||
.io_type(slcr::IoBufferType::Lvcmos33)
|
||||
.pullup(true)
|
||||
);
|
||||
});
|
||||
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
slcr.uart_rst_ctrl.reset_uart1();
|
||||
slcr.aper_clk_ctrl.enable_uart1();
|
||||
slcr.uart_clk_ctrl.enable_uart1();
|
||||
});
|
||||
let mut self_ = Uart {
|
||||
regs: regs::RegisterBlock::uart1(),
|
||||
};
|
||||
self_.configure(baudrate);
|
||||
self_
|
||||
}
|
||||
|
||||
pub fn write_byte(&mut self, value: u8) {
|
||||
while self.tx_fifo_full() {}
|
||||
|
||||
|
||||
@ -6,14 +6,24 @@ edition = "2018"
|
||||
|
||||
[dependencies]
|
||||
libboard_zynq = { path = "../libboard_zynq" }
|
||||
core_io = { version = "0.1", features = ["collections"] }
|
||||
fatfs = { version = "0.3", features = ["core_io"], default-features = false }
|
||||
log = "0.4"
|
||||
|
||||
[dependencies.core_io]
|
||||
git = "https://git.m-labs.hk/M-Labs/rs-core_io.git"
|
||||
rev = "e9d3edf027"
|
||||
features = ["collections"]
|
||||
|
||||
[dependencies.fatfs]
|
||||
git = "https://git.m-labs.hk/M-Labs/rust-fatfs.git"
|
||||
rev = "4b5e420084"
|
||||
default-features = false
|
||||
features = ["core_io"]
|
||||
|
||||
[features]
|
||||
target_zc706 = []
|
||||
target_coraz7 = []
|
||||
target_ebaz4205 = []
|
||||
target_redpitaya = []
|
||||
target_kasli_soc = []
|
||||
ipv6 = []
|
||||
fat_lfn = [ "fatfs/alloc" ]
|
||||
fat_lfn = [ "fatfs/alloc" ]
|
||||
|
||||
@ -59,6 +59,10 @@ pub fn get_addresses(cfg: &Config) -> NetAddresses {
|
||||
let mut hardware_addr = get_address_from_eeprom();
|
||||
#[cfg(feature = "target_kasli_soc")]
|
||||
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x57]);
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 57);
|
||||
|
||||
if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
|
||||
hardware_addr = addr;
|
||||
|
||||
@ -1,59 +1,60 @@
|
||||
use core::arch::asm;
|
||||
|
||||
/// The classic no-op
|
||||
#[inline]
|
||||
pub fn nop() {
|
||||
unsafe { llvm_asm!("nop" :::: "volatile") }
|
||||
unsafe { asm!("nop") }
|
||||
}
|
||||
|
||||
/// Wait For Event
|
||||
#[inline]
|
||||
pub fn wfe() {
|
||||
unsafe { llvm_asm!("wfe" :::: "volatile") }
|
||||
unsafe { asm!("wfe") }
|
||||
}
|
||||
|
||||
/// Send Event
|
||||
#[inline]
|
||||
pub fn sev() {
|
||||
unsafe { llvm_asm!("sev" :::: "volatile") }
|
||||
unsafe { asm!("sev") }
|
||||
}
|
||||
|
||||
/// Data Memory Barrier
|
||||
#[inline]
|
||||
pub fn dmb() {
|
||||
unsafe { llvm_asm!("dmb" :::: "volatile") }
|
||||
unsafe { asm!("dmb") }
|
||||
}
|
||||
|
||||
/// Data Synchronization Barrier
|
||||
#[inline]
|
||||
pub fn dsb() {
|
||||
unsafe { llvm_asm!("dsb" :::: "volatile") }
|
||||
unsafe { asm!("dsb") }
|
||||
}
|
||||
|
||||
/// Instruction Synchronization Barrier
|
||||
#[inline]
|
||||
pub fn isb() {
|
||||
unsafe { llvm_asm!("isb" :::: "volatile") }
|
||||
unsafe { asm!("isb") }
|
||||
}
|
||||
|
||||
/// Enable FIQ
|
||||
#[inline]
|
||||
pub unsafe fn enable_fiq() {
|
||||
llvm_asm!("cpsie f":::: "volatile");
|
||||
asm!("cpsie f");
|
||||
}
|
||||
|
||||
/// Enable IRQ
|
||||
#[inline]
|
||||
pub unsafe fn enable_irq() {
|
||||
llvm_asm!("cpsie i":::: "volatile");
|
||||
asm!("cpsie i");
|
||||
}
|
||||
|
||||
/// Disable IRQ, return if IRQ was originally enabled.
|
||||
#[inline]
|
||||
pub unsafe fn enter_critical() -> bool {
|
||||
let mut cpsr: u32;
|
||||
llvm_asm!(
|
||||
"mrs $0, cpsr
|
||||
cpsid i"
|
||||
: "=r"(cpsr) ::: "volatile");
|
||||
asm!(
|
||||
"mrs {}, cpsr
|
||||
cpsid i", lateout(reg) cpsr);
|
||||
(cpsr & (1 << 7)) == 0
|
||||
}
|
||||
|
||||
@ -65,18 +66,18 @@ pub unsafe fn exit_critical(enable: bool) {
|
||||
} else {
|
||||
0
|
||||
};
|
||||
llvm_asm!(
|
||||
asm!(
|
||||
"mrs r1, cpsr
|
||||
bic r1, r1, $0
|
||||
bic r1, r1, {}
|
||||
msr cpsr_c, r1"
|
||||
:: "r"(mask) : "r1");
|
||||
, in(reg) mask, out("r1") _);
|
||||
}
|
||||
|
||||
/// Exiting IRQ
|
||||
#[inline]
|
||||
pub unsafe fn exit_irq() {
|
||||
llvm_asm!("
|
||||
asm!("
|
||||
mrs r0, SPSR
|
||||
msr CPSR, r0
|
||||
" ::: "r0");
|
||||
", out("r0") _);
|
||||
}
|
||||
|
||||
@ -1,11 +1,12 @@
|
||||
use super::asm::{dmb, dsb};
|
||||
use super::l2c::*;
|
||||
use core::arch::asm;
|
||||
|
||||
/// Invalidate TLBs
|
||||
#[inline(always)]
|
||||
pub fn tlbiall() {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
|
||||
asm!("mcr p15, 0, {}, c8, c7, 0", in(reg) 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -13,7 +14,7 @@ pub fn tlbiall() {
|
||||
#[inline(always)]
|
||||
pub fn iciallu() {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
|
||||
asm!("mcr p15, 0, {}, c7, c5, 0", in(reg) 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -21,7 +22,7 @@ pub fn iciallu() {
|
||||
#[inline(always)]
|
||||
pub fn bpiall() {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
|
||||
asm!("mcr p15, 0, {}, c7, c5, 6", in(reg) 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -29,7 +30,7 @@ pub fn bpiall() {
|
||||
#[inline(always)]
|
||||
pub fn dccsw(setway: u32) {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
|
||||
asm!("mcr p15, 0, {}, c7, c10, 2", in(reg) setway);
|
||||
}
|
||||
}
|
||||
|
||||
@ -41,7 +42,7 @@ pub fn dcisw(setway: u32) {
|
||||
// also see example code (for DCCISW, but DCISW will be
|
||||
// analogous) "Example code for cache maintenance operations"
|
||||
// on pages B2-1286 and B2-1287.
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
|
||||
asm!("mcr p15, 0, {}, c7, c6, 2", in(reg) setway);
|
||||
}
|
||||
}
|
||||
|
||||
@ -49,7 +50,7 @@ pub fn dcisw(setway: u32) {
|
||||
#[inline(always)]
|
||||
pub fn dccisw(setway: u32) {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c14, 2" :: "r" (setway) :: "volatile");
|
||||
asm!("mcr p15, 0, {}, c7, c14, 2", in(reg) setway);
|
||||
}
|
||||
}
|
||||
|
||||
@ -69,7 +70,7 @@ pub fn dciall_l1() {
|
||||
|
||||
// select L1 data cache
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
|
||||
asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
|
||||
}
|
||||
|
||||
// Invalidate entire D-Cache by iterating every set and every way
|
||||
@ -104,7 +105,7 @@ pub fn dcciall_l1() {
|
||||
|
||||
// select L1 data cache
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
|
||||
asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
|
||||
}
|
||||
|
||||
// Invalidate entire D-Cache by iterating every set and every way
|
||||
@ -156,7 +157,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
|
||||
#[inline(always)]
|
||||
pub fn dccimvac(addr: usize) {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
|
||||
asm!("mcr p15, 0, {}, c7, c14, 1", in(reg) addr);
|
||||
}
|
||||
}
|
||||
|
||||
@ -198,10 +199,9 @@ pub fn dcci_slice<T>(slice: &[T]) {
|
||||
#[inline(always)]
|
||||
pub fn dccmvac(addr: usize) {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
|
||||
asm!("mcr p15, 0, {}, c7, c10, 1", in(reg) addr);
|
||||
}
|
||||
}
|
||||
|
||||
/// Data cache clean for an object.
|
||||
pub fn dcc<T>(object: &T) {
|
||||
dmb();
|
||||
@ -239,7 +239,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
|
||||
/// affecting more data than intended.
|
||||
#[inline(always)]
|
||||
pub unsafe fn dcimvac(addr: usize) {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
|
||||
asm!("mcr p15, 0, {}, c7, c6, 1", in(reg) addr);
|
||||
}
|
||||
|
||||
/// Data cache clean and invalidate for an object.
|
||||
|
||||
@ -1,7 +1,8 @@
|
||||
use core::arch::asm;
|
||||
/// Enable FPU in the current core.
|
||||
pub fn enable_fpu() {
|
||||
unsafe {
|
||||
llvm_asm!("
|
||||
asm!("
|
||||
mrc p15, 0, r1, c1, c0, 2
|
||||
orr r1, r1, (0b1111<<20)
|
||||
mcr p15, 0, r1, c1, c0, 2
|
||||
@ -9,6 +10,6 @@ pub fn enable_fpu() {
|
||||
vmrs r1, fpexc
|
||||
orr r1, r1, (1<<30)
|
||||
vmsr fpexc, r1
|
||||
":::"r1");
|
||||
", out("r1") _);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,7 +1,10 @@
|
||||
#![no_std]
|
||||
#![feature(llvm_asm, global_asm)]
|
||||
#![feature(never_type)]
|
||||
#![feature(const_fn)]
|
||||
#![feature(global_asm)]
|
||||
#![feature(asm)]
|
||||
#![allow(incomplete_features)]
|
||||
#![feature(inline_const)]
|
||||
#![feature(const_fn_trait_bound)]
|
||||
|
||||
extern crate alloc;
|
||||
|
||||
@ -17,6 +20,7 @@ pub mod sync_channel;
|
||||
mod uncached;
|
||||
pub use fpu::enable_fpu;
|
||||
pub use uncached::UncachedSlice;
|
||||
use core::arch::global_asm;
|
||||
|
||||
global_asm!(include_str!("exceptions.s"));
|
||||
|
||||
|
||||
@ -2,6 +2,7 @@ use libregister::{
|
||||
register_bit, register_bits,
|
||||
RegisterR, RegisterW, RegisterRW,
|
||||
};
|
||||
use core::arch::asm;
|
||||
|
||||
macro_rules! def_reg_r {
|
||||
($name:tt, $type: ty, $asm_instr:tt) => {
|
||||
@ -11,7 +12,7 @@ macro_rules! def_reg_r {
|
||||
#[inline]
|
||||
fn read(&self) -> Self::R {
|
||||
let mut value: u32;
|
||||
unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
|
||||
unsafe { asm!($asm_instr, lateout(reg) value) }
|
||||
value.into()
|
||||
}
|
||||
}
|
||||
@ -26,7 +27,7 @@ macro_rules! def_reg_w {
|
||||
#[inline]
|
||||
fn write(&mut self, value: Self::W) {
|
||||
let value: u32 = value.into();
|
||||
unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
|
||||
unsafe { asm!($asm_instr, in(reg) value) }
|
||||
}
|
||||
|
||||
#[inline]
|
||||
@ -71,29 +72,29 @@ macro_rules! wrap_reg {
|
||||
|
||||
/// Stack Pointer
|
||||
pub struct SP;
|
||||
def_reg_r!(SP, u32, "mov $0, sp");
|
||||
def_reg_w!(SP, u32, "mov sp, $0");
|
||||
def_reg_r!(SP, u32, "mov {}, sp");
|
||||
def_reg_w!(SP, u32, "mov sp, {}");
|
||||
|
||||
/// Link register (function call return address)
|
||||
pub struct LR;
|
||||
def_reg_r!(LR, u32, "mov $0, lr");
|
||||
def_reg_w!(LR, u32, "mov lr, $0");
|
||||
def_reg_r!(LR, u32, "mov {}, lr");
|
||||
def_reg_w!(LR, u32, "mov lr, {}");
|
||||
|
||||
pub struct VBAR;
|
||||
def_reg_r!(VBAR, u32, "mrc p15, 0, $0, c12, c0, 0");
|
||||
def_reg_w!(VBAR, u32, "mcr p15, 0, $0, c12, c0, 0");
|
||||
def_reg_r!(VBAR, u32, "mrc p15, 0, {}, c12, c0, 0");
|
||||
def_reg_w!(VBAR, u32, "mcr p15, 0, {}, c12, c0, 0");
|
||||
|
||||
pub struct MVBAR;
|
||||
def_reg_r!(MVBAR, u32, "mrc p15, 0, $0, c12, c0, 1");
|
||||
def_reg_w!(MVBAR, u32, "mcr p15, 0, $0, c12, c0, 1");
|
||||
def_reg_r!(MVBAR, u32, "mrc p15, 0, {}, c12, c0, 1");
|
||||
def_reg_w!(MVBAR, u32, "mcr p15, 0, {}, c12, c0, 1");
|
||||
|
||||
pub struct HVBAR;
|
||||
def_reg_r!(HVBAR, u32, "mrc p15, 4, $0, c12, c0, 0");
|
||||
def_reg_w!(HVBAR, u32, "mcr p15, 4, $0, c12, c0, 0");
|
||||
def_reg_r!(HVBAR, u32, "mrc p15, 4, {}, c12, c0, 0");
|
||||
def_reg_w!(HVBAR, u32, "mcr p15, 4, {}, c12, c0, 0");
|
||||
|
||||
/// Multiprocess Affinity Register
|
||||
pub struct MPIDR;
|
||||
def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, $0, c0, c0, 5");
|
||||
def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, {}, c0, c0, 5");
|
||||
wrap_reg!(mpidr);
|
||||
register_bits!(mpidr,
|
||||
/// CPU core index
|
||||
@ -106,15 +107,15 @@ register_bit!(mpidr,
|
||||
u, 30);
|
||||
|
||||
pub struct DFAR;
|
||||
def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
|
||||
def_reg_r!(DFAR, u32, "mrc p15, 0, {}, c6, c0, 0");
|
||||
|
||||
pub struct DFSR;
|
||||
def_reg_r!(DFSR, u32, "mrc p15, 0, $0, c5, c0, 0");
|
||||
def_reg_r!(DFSR, u32, "mrc p15, 0, {}, c5, c0, 0");
|
||||
|
||||
pub struct SCTLR;
|
||||
wrap_reg!(sctlr);
|
||||
def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, $0, c1, c0, 0");
|
||||
def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, $0, c1, c0, 0");
|
||||
def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, {}, c1, c0, 0");
|
||||
def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, {}, c1, c0, 0");
|
||||
register_bit!(sctlr,
|
||||
/// Enables MMU
|
||||
m, 0);
|
||||
@ -147,8 +148,8 @@ register_bit!(sctlr,
|
||||
/// Auxiliary Control Register
|
||||
pub struct ACTLR;
|
||||
wrap_reg!(actlr);
|
||||
def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, $0, c1, c0, 1");
|
||||
def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, $0, c1, c0, 1");
|
||||
def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, {}, c1, c0, 1");
|
||||
def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, {}, c1, c0, 1");
|
||||
// SMP bit
|
||||
register_bit!(actlr, parity_on, 9);
|
||||
register_bit!(actlr, alloc_one_way, 8);
|
||||
@ -183,17 +184,17 @@ impl ACTLR {
|
||||
|
||||
/// Domain Access Control Register
|
||||
pub struct DACR;
|
||||
def_reg_r!(DACR, u32, "mrc p15, 0, $0, c3, c0, 0");
|
||||
def_reg_w!(DACR, u32, "mcr p15, 0, $0, c3, c0, 0");
|
||||
def_reg_r!(DACR, u32, "mrc p15, 0, {}, c3, c0, 0");
|
||||
def_reg_w!(DACR, u32, "mcr p15, 0, {}, c3, c0, 0");
|
||||
|
||||
/// Translation Table Base Register 0
|
||||
pub struct TTBR0;
|
||||
/// Translation Table Base Register 1
|
||||
pub struct TTBR1;
|
||||
def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, $0, c2, c0, 0");
|
||||
def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, $0, c2, c0, 0");
|
||||
def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, $0, c2, c0, 1");
|
||||
def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, $0, c2, c0, 1");
|
||||
def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, {}, c2, c0, 0");
|
||||
def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, {}, c2, c0, 0");
|
||||
def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, {}, c2, c0, 1");
|
||||
def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, {}, c2, c0, 1");
|
||||
wrap_reg!(ttbr);
|
||||
register_bits!(ttbr, table_base, u32, 14, 31);
|
||||
register_bit!(ttbr, irgn0, 6);
|
||||
|
||||
@ -172,13 +172,15 @@ impl<'a, T> Iterator for Receiver<'a, T> where T: Clone {
|
||||
|
||||
#[macro_export]
|
||||
/// Macro for initializing the sync_channel with static buffer and indexes.
|
||||
/// Note that this requires `#![feature(const_in_array_repeat_expressions)]`
|
||||
macro_rules! sync_channel {
|
||||
($t: ty, $cap: expr) => {
|
||||
{
|
||||
use core::sync::atomic::{AtomicUsize, AtomicPtr};
|
||||
use $crate::sync_channel::{Sender, Receiver};
|
||||
static LIST: [AtomicPtr<$t>; $cap + 1] = [AtomicPtr::new(core::ptr::null_mut()); $cap + 1];
|
||||
const fn new_atomic() -> AtomicPtr<$t> {
|
||||
AtomicPtr::new(core::ptr::null_mut())
|
||||
}
|
||||
static LIST: [AtomicPtr<$t>; $cap + 1] = [const { new_atomic() }; $cap + 1];
|
||||
static WRITE: AtomicUsize = AtomicUsize::new(0);
|
||||
static READ: AtomicUsize = AtomicUsize::new(0);
|
||||
(Sender::new(&LIST, &WRITE, &READ), Receiver::new(&LIST, &WRITE, &READ))
|
||||
|
||||
@ -8,6 +8,7 @@ edition = "2018"
|
||||
[features]
|
||||
target_zc706 = ["libboard_zynq/target_zc706"]
|
||||
target_coraz7 = ["libboard_zynq/target_coraz7"]
|
||||
target_ebaz4205 = ["libboard_zynq/target_ebaz4205"]
|
||||
target_redpitaya = ["libboard_zynq/target_redpitaya"]
|
||||
target_kasli_soc = ["libboard_zynq/target_kasli_soc"]
|
||||
panic_handler = []
|
||||
@ -19,7 +20,7 @@ default = ["panic_handler", "dummy_irq_handler", "dummy_fiq_handler"]
|
||||
|
||||
[dependencies]
|
||||
r0 = "1"
|
||||
compiler_builtins = "=0.1.39"
|
||||
compiler_builtins = "=0.1.49"
|
||||
linked_list_allocator = { version = "0.8", default-features = false, features = ["const_mut_refs"] }
|
||||
libregister = { path = "../libregister" }
|
||||
libcortex_a9 = { path = "../libcortex_a9" }
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
use r0::zero_bss;
|
||||
use core::ptr::write_volatile;
|
||||
use core::arch::asm;
|
||||
use libregister::{
|
||||
VolatileCell,
|
||||
RegisterR, RegisterRW,
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
use libregister::{RegisterR, RegisterW};
|
||||
use libcortex_a9::{regs::{DFSR, MPIDR, VBAR}, interrupt_handler};
|
||||
use libboard_zynq::{println, stdio};
|
||||
use core::arch::asm;
|
||||
|
||||
pub fn set_vector_table(base_addr: u32){
|
||||
VBAR.write(base_addr);
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
#![feature(alloc_error_handler)]
|
||||
#![feature(panic_info_message)]
|
||||
#![feature(naked_functions)]
|
||||
#![feature(global_asm)]
|
||||
#![feature(asm)]
|
||||
|
||||
pub extern crate alloc;
|
||||
|
||||
33
openocd/ebaz4205.cfg
Normal file
33
openocd/ebaz4205.cfg
Normal file
@ -0,0 +1,33 @@
|
||||
# The contents of this file are partially dependend on
|
||||
# the adapter that you have. Please modify accordingly.
|
||||
adapter driver ftdi
|
||||
ftdi vid_pid 0x0403 0x6010
|
||||
ftdi channel 0
|
||||
# Every pin set as high impedance except TCK, TDI, TDO and TMS
|
||||
ftdi layout_init 0x0088 0x008b
|
||||
|
||||
# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
|
||||
# This choice is arbitrary. Use other GPIO pin if desired.
|
||||
ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
|
||||
|
||||
transport select jtag
|
||||
adapter speed 10000
|
||||
|
||||
set PL_TAPID 0x13722093
|
||||
set SMP 1
|
||||
|
||||
source ./zynq-7000.cfg
|
||||
|
||||
reset_config srst_only srst_open_drain
|
||||
adapter srst pulse_width 250
|
||||
adapter srst delay 400
|
||||
|
||||
source ./common.cfg
|
||||
|
||||
reset halt
|
||||
|
||||
# Disable MMU
|
||||
targets $_TARGETNAME_1
|
||||
arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]
|
||||
targets $_TARGETNAME_0
|
||||
arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]
|
||||
@ -8,6 +8,7 @@ edition = "2018"
|
||||
[features]
|
||||
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
|
||||
target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
|
||||
target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205"]
|
||||
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
|
||||
target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
|
||||
default = ["target_zc706"]
|
||||
@ -15,10 +16,14 @@ default = ["target_zc706"]
|
||||
[dependencies]
|
||||
log = "0.4"
|
||||
byteorder = { version = "1.3", default-features = false }
|
||||
core_io = { version = "0.1", features = ["collections"] }
|
||||
|
||||
libboard_zynq = { path = "../libboard_zynq" }
|
||||
libsupport_zynq = { path = "../libsupport_zynq" }
|
||||
libcortex_a9 = { path = "../libcortex_a9" }
|
||||
libregister = { path = "../libregister" }
|
||||
libconfig = { path = "../libconfig" }
|
||||
|
||||
[dependencies.core_io]
|
||||
git = "https://git.m-labs.hk/M-Labs/rs-core_io.git"
|
||||
rev = "e9d3edf027"
|
||||
features = ["collections"]
|
||||
|
||||
|
||||
@ -80,12 +80,15 @@ pub fn main_core0() {
|
||||
);
|
||||
info!("Simple Zynq Loader starting...");
|
||||
|
||||
#[cfg(not(feature = "target_kasli_soc"))]
|
||||
#[cfg(not(any(feature = "target_kasli_soc", feature = "target_ebaz4205")))]
|
||||
const CPU_FREQ: u32 = 800_000_000;
|
||||
|
||||
#[cfg(feature = "target_kasli_soc")]
|
||||
const CPU_FREQ: u32 = 1_000_000_000;
|
||||
|
||||
#[cfg(feature = "target_ebaz4205")]
|
||||
const CPU_FREQ: u32 = 666_666_666;
|
||||
|
||||
ArmPll::setup(2 * CPU_FREQ);
|
||||
Clocks::set_cpu_freq(CPU_FREQ);
|
||||
IoPll::setup(1_000_000_000);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user