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srenblad:improve_tcp_stream
srenblad:change_to_core2
srenblad:up_rust_llvm_versions
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srenblad:bump_to_latest
srenblad:improve_tcp_stream
srenblad:change_to_core2
srenblad:up_rust_llvm_versions
srenblad:add_llvm_11
srenblad:esavkin/reboot_support

10 Commits
add_llvm_1 ... master

Author SHA1 Message Date
Sebastien Bourdeauducq 12975de2e1 flake: add missing attributes on rustc (for nixpkgs-unstable compat) 2024-11-16 17:31:34 +08:00
Sebastien Bourdeauducq 8c404829ef flake: update nixpkgs 2024-11-16 17:15:03 +08:00
Sebastien Bourdeauducq 8f041b017c switch to oxalica rust overlay 2024-11-16 17:14:37 +08:00
newell 5815baf88b Reorder Status.get_link to check for higher speeds before slower. 2024-11-15 13:09:17 -08:00
newell cc20478d91 Add i2c support 2024-10-04 23:38:28 -07:00
Sebastien Bourdeauducq 5ef3016554 flake: update dependencies 2024-09-30 14:15:10 +08:00
newell 6a45a0dfd0 ebaz4205 support 
Co-authored-by: newell <newell.jensen@gmail.com>
Co-committed-by: newell <newell.jensen@gmail.com>
 2024-09-30 14:08:58 +08:00
Sebastien Bourdeauducq b2b3e5c933 flake: update dependencies 2024-07-09 17:03:22 +02:00
Simon Renblad 0efbbe39fe llvm: patch for artiq-zynq release-7 2024-06-06 14:06:56 +08:00
Sebastien Bourdeauducq 51b8111e79 flake: move to nixos 24.05 2024-05-28 17:37:50 +08:00
25 changed files with 303 additions and 125 deletions
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1
experiments/Cargo.toml
View File

@ -8,6 +8,7 @@ edition = "2018"
[features] [features]
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"] target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"] target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205"]
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"] target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"] target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"]
default = ["target_zc706"] default = ["target_zc706"]

1
experiments/src/main.rs
View File

@ -116,6 +116,7 @@ pub fn main_core0() {
#[cfg(any( #[cfg(any(
feature = "target_zc706", feature = "target_zc706",
feature = "target_ebaz4205",
feature = "target_redpitaya", feature = "target_redpitaya",
feature = "target_kasli_soc", feature = "target_kasli_soc",
))] ))]

49
flake.lock
View File

@ -1,41 +1,46 @@
{ {
"nodes": { "nodes": {
"mozilla-overlay": {
"flake": false,
"locked": {
"lastModified": 1704373101,
"narHash": "sha256-+gi59LRWRQmwROrmE1E2b3mtocwueCQqZ60CwLG+gbg=",
"owner": "mozilla",
"repo": "nixpkgs-mozilla",
"rev": "9b11a87c0cc54e308fa83aac5b4ee1816d5418a2",
"type": "github"
},
"original": {
"owner": "mozilla",
"repo": "nixpkgs-mozilla",
"type": "github"
}
},
"nixpkgs": { "nixpkgs": {
"locked": { "locked": {
"lastModified": 1716330097, "lastModified": 1731652201,
"narHash": "sha256-8BO3B7e3BiyIDsaKA0tY8O88rClYRTjvAp66y+VBUeU=", "narHash": "sha256-XUO0JKP1hlww0d7mm3kpmIr4hhtR4zicg5Wwes9cPMg=",
"owner": "NixOS", "owner": "NixOS",
"repo": "nixpkgs", "repo": "nixpkgs",
"rev": "5710852ba686cc1fd0d3b8e22b3117d43ba374c2", "rev": "c21b77913ea840f8bcf9adf4c41cecc2abffd38d",
"type": "github" "type": "github"
}, },
"original": { "original": {
"owner": "NixOS", "owner": "NixOS",
"ref": "nixos-unstable", "ref": "nixos-24.05",
"repo": "nixpkgs", "repo": "nixpkgs",
"type": "github" "type": "github"
} }
}, },
"root": { "root": {
"inputs": { "inputs": {
"mozilla-overlay": "mozilla-overlay", "nixpkgs": "nixpkgs",
"nixpkgs": "nixpkgs" "rust-overlay": "rust-overlay"
}
},
"rust-overlay": {
"inputs": {
"nixpkgs": [
"nixpkgs"
]
},
"locked": {
"lastModified": 1719454714,
"narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
"owner": "oxalica",
"repo": "rust-overlay",
"rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
"type": "github"
},
"original": {
"owner": "oxalica",
"ref": "snapshot/2024-08-01",
"repo": "rust-overlay",
"type": "github"
} }
} }
}, },

37
flake.nix
View File

@ -1,30 +1,29 @@
{ {
description = "Bare-metal Rust on Zynq-7000"; description = "Bare-metal Rust on Zynq-7000";
inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-unstable; inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.05;
inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; }; inputs.rust-overlay = {
url = "github:oxalica/rust-overlay?ref=snapshot/2024-08-01";
inputs.nixpkgs.follows = "nixpkgs";
};
outputs = { self, nixpkgs, mozilla-overlay }: outputs = { self, nixpkgs, rust-overlay }:
let let
pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) crosspkgs-overlay ]; }; pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import rust-overlay) crosspkgs-overlay ]; };
rustManifest = pkgs.fetchurl { rust = pkgs.rust-bin.nightly."2021-01-28".default.override {
url = "https://static.rust-lang.org/dist/2021-01-29/channel-rust-nightly.toml"; extensions = [ "rust-src" ];
sha256 = "sha256-EZKgw89AH4vxaJpUHmIMzMW/80wAFQlfcxRoBD9nz0c="; targets = [ ];
}; };
rustTargets = []; rustPlatform = pkgs.makeRustPlatform {
rustChannelOfTargets = _channel: _date: targets: rustc = rust // {
(pkgs.lib.rustLib.fromManifestFile rustManifest { # https://github.com/oxalica/rust-overlay/commit/c48c2d76b68dd9ede0815fec53479375c61af857
inherit (pkgs) stdenv lib fetchurl patchelf; targetPlatforms = pkgs.lib.platforms.all;
}).rust.override { tier1TargetPlatforms = pkgs.lib.platforms.all;
inherit targets; badTargetPlatforms = [ ];
extensions = ["rust-src"];
}; };
rust = rustChannelOfTargets "nightly" null rustTargets;
rustPlatform = pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
rustc = rust;
cargo = rust; cargo = rust;
}); };
# https://doc.rust-lang.org/rustc/linker-plugin-lto.html#toolchain-compatibility # https://doc.rust-lang.org/rustc/linker-plugin-lto.html#toolchain-compatibility
llvmPackages_11 = pkgs.recurseIntoAttrs (pkgs.callPackage (import ./llvm/11) ({ llvmPackages_11 = pkgs.recurseIntoAttrs (pkgs.callPackage (import ./llvm/11) ({
@ -142,7 +141,7 @@
"${target}-experiments" = build-crate "${target}-experiments" "experiments" "target_${target}"; "${target}-experiments" = build-crate "${target}-experiments" "experiments" "target_${target}";
"${target}-szl" = build-crate "${target}-szl" "szl" "target_${target}"; "${target}-szl" = build-crate "${target}-szl" "szl" "target_${target}";
}; };
targets = ["zc706" "coraz7" "redpitaya" "kasli_soc"]; targets = ["zc706" "coraz7" "redpitaya" "kasli_soc" "ebaz4205"];
allTargetCrates = (builtins.foldl' (results: target: allTargetCrates = (builtins.foldl' (results: target:
results // targetCrates target results // targetCrates target
) {} targets); ) {} targets);

1
libboard_zynq/Cargo.toml
View File

@ -8,6 +8,7 @@ edition = "2018"
[features] [features]
target_zc706 = [] target_zc706 = []
target_coraz7 = [] target_coraz7 = []
target_ebaz4205 = []
target_redpitaya = [] target_redpitaya = []
target_kasli_soc = [] target_kasli_soc = []
ipv6 = [ "smoltcp/proto-ipv6" ] ipv6 = [ "smoltcp/proto-ipv6" ]

6
libboard_zynq/src/clocks/mod.rs
View File

@ -1,3 +1,5 @@
use core::unimplemented;
use libregister::{RegisterR, RegisterRW}; use libregister::{RegisterR, RegisterRW};
use super::slcr; use super::slcr;
pub use slcr::ArmPllSource; pub use slcr::ArmPllSource;
@ -101,6 +103,8 @@ impl Clocks {
self.ddr, self.ddr,
slcr::PllSource::IoPll => slcr::PllSource::IoPll =>
self.io, self.io,
slcr::PllSource::Emio =>
unimplemented!(),
}; };
pll / u32::from(uart_clk_ctrl.divisor()) pll / u32::from(uart_clk_ctrl.divisor())
} }
@ -115,6 +119,8 @@ impl Clocks {
self.ddr, self.ddr,
slcr::PllSource::IoPll => slcr::PllSource::IoPll =>
self.io, self.io,
slcr::PllSource::Emio =>
unimplemented!(),
}; };
pll / u32::from(sdio_clk_ctrl.divisor()) pll / u32::from(sdio_clk_ctrl.divisor())
} }

2
libboard_zynq/src/clocks/source.rs
View File

@ -6,6 +6,8 @@ use super::slcr;
pub const PS_CLK: u32 = 33_333_333; pub const PS_CLK: u32 = 33_333_333;
#[cfg(feature = "target_coraz7")] #[cfg(feature = "target_coraz7")]
pub const PS_CLK: u32 = 50_000_000; pub const PS_CLK: u32 = 50_000_000;
#[cfg(feature = "target_ebaz4205")]
pub const PS_CLK: u32 = 33_333_333;
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
pub const PS_CLK: u32 = 33_333_333; pub const PS_CLK: u32 = 33_333_333;
#[cfg(feature = "target_kasli_soc")] #[cfg(feature = "target_kasli_soc")]

122
libboard_zynq/src/ddr/mod.rs
View File

@ -16,6 +16,10 @@ const DDR_FREQ: u32 = 666_666_666;
/// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz /// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
const DDR_FREQ: u32 = 525_000_000; const DDR_FREQ: u32 = 525_000_000;
#[cfg(feature = "target_ebaz4205")]
/// EtronTech Memory EM6GD16EWKG-12H: 800 MHz DDR3 at 533 MHz
const DDR_FREQ: u32 = 533_333_333;
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz /// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
const DDR_FREQ: u32 = 533_333_333; const DDR_FREQ: u32 = 533_333_333;
@ -147,22 +151,23 @@ impl DdrRam {
.output_en(slcr::DdriobOutputEn::Obuf); .output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let data1_config = data0_config.clone(); let data1_config = data0_config.clone();
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))] #[cfg(any(
feature = "target_coraz7",
feature = "target_ebaz4205",
feature = "target_redpitaya",
feature = "target_kasli_soc",
))]
let data0_config = slcr::DdriobConfig::zeroed() let data0_config = slcr::DdriobConfig::zeroed()
.inp_type(slcr::DdriobInputType::VrefDifferential) .inp_type(slcr::DdriobInputType::VrefDifferential)
.term_en(true) .term_en(true)
.dci_type(slcr::DdriobDciType::Termination) .dci_type(slcr::DdriobDciType::Termination)
.output_en(slcr::DdriobOutputEn::Obuf); .output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))] #[cfg(any(
let data1_config = slcr::DdriobConfig::zeroed() feature = "target_coraz7",
.pullup_en(true); feature = "target_ebaz4205",
#[cfg(feature = "target_redpitaya")] feature = "target_redpitaya",
let data0_config = slcr::DdriobConfig::zeroed() feature = "target_kasli_soc",
.inp_type(slcr::DdriobInputType::VrefDifferential) ))]
.term_en(true)
.dci_type(slcr::DdriobDciType::Termination)
.output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_redpitaya")]
let data1_config = slcr::DdriobConfig::zeroed() let data1_config = slcr::DdriobConfig::zeroed()
.pullup_en(true); .pullup_en(true);
slcr.ddriob_data0.write(data0_config); slcr.ddriob_data0.write(data0_config);
@ -176,22 +181,23 @@ impl DdrRam {
.output_en(slcr::DdriobOutputEn::Obuf); .output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let diff1_config = diff0_config.clone(); let diff1_config = diff0_config.clone();
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))] #[cfg(any(
feature = "target_coraz7",
feature = "target_ebaz4205",
feature = "target_redpitaya",
feature = "target_kasli_soc",
))]
let diff0_config = slcr::DdriobConfig::zeroed() let diff0_config = slcr::DdriobConfig::zeroed()
.inp_type(slcr::DdriobInputType::Differential) .inp_type(slcr::DdriobInputType::Differential)
.term_en(true) .term_en(true)
.dci_type(slcr::DdriobDciType::Termination) .dci_type(slcr::DdriobDciType::Termination)
.output_en(slcr::DdriobOutputEn::Obuf); .output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))] #[cfg(any(
let diff1_config = slcr::DdriobConfig::zeroed() feature = "target_coraz7",
.pullup_en(true); feature = "target_ebaz4205",
#[cfg(feature = "target_redpitaya")] feature = "target_redpitaya",
let diff0_config = slcr::DdriobConfig::zeroed() feature = "target_kasli_soc",
.inp_type(slcr::DdriobInputType::Differential) ))]
.term_en(true)
.dci_type(slcr::DdriobDciType::Termination)
.output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_redpitaya")]
let diff1_config = slcr::DdriobConfig::zeroed() let diff1_config = slcr::DdriobConfig::zeroed()
.pullup_en(true); .pullup_en(true);
slcr.ddriob_diff0.write(diff0_config); slcr.ddriob_diff0.write(diff0_config);
@ -210,7 +216,12 @@ impl DdrRam {
slcr.ddriob_drive_slew_clock.write(0x00F9861C); slcr.ddriob_drive_slew_clock.write(0x00F9861C);
} }
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))] #[cfg(any(
feature = "target_coraz7",
feature = "target_ebaz4205",
feature = "target_redpitaya",
feature = "target_kasli_soc",
))]
slcr.ddriob_ddr_ctrl.modify(|_, w| w slcr.ddriob_ddr_ctrl.modify(|_, w| w
.vref_int_en(false) .vref_int_en(false)
.vref_ext_en_lower(true) .vref_ext_en_lower(true)
@ -224,13 +235,6 @@ impl DdrRam {
.vref_ext_en_lower(false) .vref_ext_en_lower(false)
.vref_ext_en_upper(false) .vref_ext_en_upper(false)
); );
#[cfg(feature = "target_redpitaya")]
slcr.ddriob_ddr_ctrl.modify(|_, w| w
.vref_int_en(false)
.vref_ext_en_lower(true)
.vref_ext_en_upper(false)
.refio_en(true)
);
}); });
} }
@ -242,6 +246,13 @@ impl DdrRam {
.t_rfc_min(0x9e) .t_rfc_min(0x9e)
.post_selfref_gap_x32(0x10) .post_selfref_gap_x32(0x10)
); );
#[cfg(feature = "target_ebaz4205")]
self.regs.dram_param0.write(
regs::DramParam0::zeroed()
.t_rc(0x1a)
.t_rfc_min(0x56)
.post_selfref_gap_x32(0x10)
);
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
self.regs.dram_param0.write( self.regs.dram_param0.write(
regs::DramParam0::zeroed() regs::DramParam0::zeroed()
@ -256,6 +267,12 @@ impl DdrRam {
.t_rfc_min(0x56) .t_rfc_min(0x56)
.post_selfref_gap_x32(0x10) .post_selfref_gap_x32(0x10)
); );
#[cfg(feature = "target_ebaz4205")]
self.regs.dram_param1.modify(
|_, w| w
.t_faw(0x16)
.t_ras_min(0x13)
);
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
self.regs.dram_param1.modify( self.regs.dram_param1.modify(
|_, w| w |_, w| w
@ -277,6 +294,11 @@ impl DdrRam {
.rd2pre(0x4) .rd2pre(0x4)
.t_rcd(0x7) .t_rcd(0x7)
); );
#[cfg(feature = "target_ebaz4205")]
self.regs.dram_param3.modify(
|_, w| w
.t_rp(7)
);
#[cfg(feature = "target_redpitaya")] #[cfg(feature = "target_redpitaya")]
self.regs.dram_param3.modify( self.regs.dram_param3.modify(
|_, w| w |_, w| w
@ -298,19 +320,21 @@ impl DdrRam {
.emr(0x4) .emr(0x4)
); );
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))] #[cfg(any(
feature = "target_coraz7",
feature = "target_ebaz4205",
feature = "target_redpitaya",
feature = "target_kasli_soc",
))]
self.regs.phy_configs[2].modify( self.regs.phy_configs[2].modify(
|_, w| w.data_slice_in_use(false) |_, w| w.data_slice_in_use(false)
); );
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))] #[cfg(any(
self.regs.phy_configs[3].modify( feature = "target_coraz7",
|_, w| w.data_slice_in_use(false) feature = "target_ebaz4205",
); feature = "target_redpitaya",
#[cfg(feature = "target_redpitaya")] feature = "target_kasli_soc",
self.regs.phy_configs[2].modify( ))]
|_, w| w.data_slice_in_use(false)
);
#[cfg(feature = "target_redpitaya")]
self.regs.phy_configs[3].modify( self.regs.phy_configs[3].modify(
|_, w| w.data_slice_in_use(false) |_, w| w.data_slice_in_use(false)
); );
@ -354,7 +378,11 @@ impl DdrRam {
.gatelvl_init_ratio(0xee) .gatelvl_init_ratio(0xee)
); );
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))] #[cfg(any(
feature = "target_coraz7",
feature = "target_ebaz4205",
feature = "target_kasli_soc"),
)]
self.regs.reg_64.modify( self.regs.reg_64.modify(
|_, w| w |_, w| w
.phy_ctrl_slave_ratio(0x100) .phy_ctrl_slave_ratio(0x100)
@ -390,9 +418,12 @@ impl DdrRam {
fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) { fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let width = regs::DataBusWidth::Width32bit; let width = regs::DataBusWidth::Width32bit;
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))] #[cfg(any(
let width = regs::DataBusWidth::Width16bit; feature = "target_coraz7",
#[cfg(feature = "target_redpitaya")] feature = "target_ebaz4205",
feature = "target_redpitaya",
feature = "target_kasli_soc",
))]
let width = regs::DataBusWidth::Width16bit; let width = regs::DataBusWidth::Width16bit;
self.regs.ddrc_ctrl.modify(|_, w| w self.regs.ddrc_ctrl.modify(|_, w| w
.soft_rstb(false) .soft_rstb(false)
@ -410,6 +441,7 @@ impl DdrRam {
} }
#[cfg(any( #[cfg(any(
feature = "target_coraz7", feature = "target_coraz7",
feature = "target_ebaz4205",
feature = "target_redpitaya", feature = "target_redpitaya",
feature = "target_kasli_soc", feature = "target_kasli_soc",
))] ))]
@ -450,6 +482,8 @@ impl DdrRam {
feature = "target_kasli_soc", feature = "target_kasli_soc",
))] ))]
let megabytes = 512; let megabytes = 512;
#[cfg(feature = "target_ebaz4205")]
let megabytes = 256;
megabytes * 1024 * 1024 megabytes * 1024 * 1024
} }

15
libboard_zynq/src/eth/mod.rs
View File

@ -65,17 +65,31 @@ impl Gem for Gem0 {
slcr.gem0_clk_ctrl.write( slcr.gem0_clk_ctrl.write(
// 0x0050_0801: 8, 5: 100 Mb/s // 0x0050_0801: 8, 5: 100 Mb/s
// ...: 8, 1: 1000 Mb/s // ...: 8, 1: 1000 Mb/s
#[cfg(not(feature = "target_ebaz4205"))]
slcr::GemClkCtrl::zeroed() slcr::GemClkCtrl::zeroed()
.clkact(true) .clkact(true)
.srcsel(slcr::PllSource::IoPll) .srcsel(slcr::PllSource::IoPll)
.divisor(divisor0 as u8) .divisor(divisor0 as u8)
.divisor1(divisor1 as u8),
// ebaz4205 -- EMIO
#[cfg(feature = "target_ebaz4205")]
slcr::GemClkCtrl::zeroed()
.clkact(true)
.srcsel(slcr::PllSource::Emio)
.divisor(divisor0 as u8)
.divisor1(divisor1 as u8) .divisor1(divisor1 as u8)
); );
// Enable gem0 recv clock // Enable gem0 recv clock
slcr.gem0_rclk_ctrl.write( slcr.gem0_rclk_ctrl.write(
// 0x0000_0801 // 0x0000_0801
#[cfg(not(feature = "target_ebaz4205"))]
slcr::RclkCtrl::zeroed()
.clkact(true),
// ebaz4205 -- EMIO
#[cfg(feature = "target_ebaz4205")]
slcr::RclkCtrl::zeroed() slcr::RclkCtrl::zeroed()
.clkact(true) .clkact(true)
.srcsel(true)
); );
}); });
} }
@ -154,6 +168,7 @@ pub struct Eth<GEM: Gem, RX, TX> {
impl Eth<Gem0, (), ()> { impl Eth<Gem0, (), ()> {
pub fn eth0(macaddr: [u8; 6]) -> Self { pub fn eth0(macaddr: [u8; 6]) -> Self {
#[cfg(not(feature = "target_ebaz4205"))]
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
// Manual example: 0x0000_1280 // Manual example: 0x0000_1280
// MDIO // MDIO

7
libboard_zynq/src/eth/phy/mod.rs
View File

@ -83,6 +83,7 @@ pub struct Phy {
const OUI_MARVELL: u32 = 0x005043; const OUI_MARVELL: u32 = 0x005043;
const OUI_REALTEK: u32 = 0x000732; const OUI_REALTEK: u32 = 0x000732;
const OUI_LANTIQ : u32 = 0x355969; const OUI_LANTIQ : u32 = 0x355969;
const OUI_ICPLUS : u32 = 0x0090c3;
//only change pages on Kasli-SoC's Marvel 88E11xx //only change pages on Kasli-SoC's Marvel 88E11xx
#[cfg(feature="target_kasli_soc")] #[cfg(feature="target_kasli_soc")]
@ -117,6 +118,12 @@ impl Phy {
model: 0, model: 0,
.. ..
}) => true, }) => true,
Some(PhyIdentifier {
oui: OUI_ICPLUS,
// IP101G-DS-R01
model: 5,
rev: 4,
}) => true,
_ => false, _ => false,
} }
}).map(|addr| Phy { addr }) }).map(|addr| Phy { addr })

32
libboard_zynq/src/eth/phy/status.rs
View File

@ -55,12 +55,22 @@ impl Status {
pub fn get_link(&self) -> Option<Link> { pub fn get_link(&self) -> Option<Link> {
if ! self.link_status() { if ! self.link_status() {
None None
} else if self.cap_10base_t_half() { } else if self.cap_100base_tx_full() {
Some(Link { Some(Link {
speed: LinkSpeed::S10, speed: LinkSpeed::S100,
duplex: LinkDuplex::Full,
})
} else if self.cap_100base_tx_half() {
Some(Link {
speed: LinkSpeed::S100,
duplex: LinkDuplex::Half, duplex: LinkDuplex::Half,
}) })
} else if self.cap_10base_t_full() { } else if self.cap_100base_t4() {
Some(Link {
speed: LinkSpeed::S100,
duplex: LinkDuplex::Half,
})
} else if self.cap_10base_t2_full() {
Some(Link { Some(Link {
speed: LinkSpeed::S10, speed: LinkSpeed::S10,
duplex: LinkDuplex::Full, duplex: LinkDuplex::Full,
@ -70,26 +80,16 @@ impl Status {
speed: LinkSpeed::S10, speed: LinkSpeed::S10,
duplex: LinkDuplex::Half, duplex: LinkDuplex::Half,
}) })
} else if self.cap_10base_t2_full() { } else if self.cap_10base_t_full() {
Some(Link { Some(Link {
speed: LinkSpeed::S10, speed: LinkSpeed::S10,
duplex: LinkDuplex::Full, duplex: LinkDuplex::Full,
}) })
} else if self.cap_100base_t4() { } else if self.cap_10base_t_half() {
Some(Link { Some(Link {
speed: LinkSpeed::S100, speed: LinkSpeed::S10,
duplex: LinkDuplex::Half, duplex: LinkDuplex::Half,
}) })
} else if self.cap_100base_tx_half() {
Some(Link {
speed: LinkSpeed::S100,
duplex: LinkDuplex::Half,
})
} else if self.cap_100base_tx_full() {
Some(Link {
speed: LinkSpeed::S100,
duplex: LinkDuplex::Full,
})
} else { } else {
None None
} }

6
libboard_zynq/src/i2c/eeprom.rs
View File

@ -4,6 +4,7 @@ use embedded_hal::timer::CountDown;
pub struct EEPROM<'a> { pub struct EEPROM<'a> {
i2c: &'a mut I2c, i2c: &'a mut I2c,
#[cfg(not(feature = "target_ebaz4205"))]
port: u8, port: u8,
address: u8, address: u8,
page_size: u8, page_size: u8,
@ -46,6 +47,11 @@ impl<'a> EEPROM<'a> {
Ok(()) Ok(())
} }
#[cfg(feature = "target_ebaz4205")]
fn select(&mut self) -> Result<(), &'static str> {
Ok(())
}
/// Random read /// Random read
pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> { pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> {
self.select()?; self.select()?;

8
libboard_zynq/src/i2c/mod.rs
View File

@ -2,10 +2,13 @@
mod regs; mod regs;
pub mod eeprom; pub mod eeprom;
#[cfg(not(feature = "target_ebaz4205"))]
use super::slcr; use super::slcr;
use super::time::Microseconds; use super::time::Microseconds;
use embedded_hal::timer::CountDown; use embedded_hal::timer::CountDown;
use libregister::{RegisterR, RegisterRW, RegisterW}; use libregister::{RegisterR, RegisterRW};
#[cfg(not(feature = "target_ebaz4205"))]
use libregister::RegisterW;
#[cfg(feature = "target_kasli_soc")] #[cfg(feature = "target_kasli_soc")]
use log::info; use log::info;
@ -22,9 +25,10 @@ pub struct I2c {
} }
impl I2c { impl I2c {
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
pub fn i2c0() -> Self { pub fn i2c0() -> Self {
// Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51 // Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
#[cfg(not(feature = "target_ebaz4205"))]
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
// SCL // SCL
slcr.mio_pin_50.write( slcr.mio_pin_50.write(

27
libboard_zynq/src/i2c/regs.rs
View File

@ -21,6 +21,7 @@ use libregister::{
// Current compatibility: // Current compatibility:
// zc706: GPIO 50, 51 == SCL, SDA // zc706: GPIO 50, 51 == SCL, SDA
// kasli_soc: GPIO 50, 51 == SCL, SDA; GPIO 33 == I2C_SW_RESET // kasli_soc: GPIO 50, 51 == SCL, SDA; GPIO 33 == I2C_SW_RESET
// ebaz4205: GPIO (EMIO)
pub struct RegisterBlock { pub struct RegisterBlock {
pub gpio_output_mask: &'static mut GPIOOutputMask, pub gpio_output_mask: &'static mut GPIOOutputMask,
@ -48,17 +49,17 @@ register!(gpio_output_mask,
/// MASK_DATA_1_MSW: /// MASK_DATA_1_MSW:
/// Maskable output data for MIO[53:48] /// Maskable output data for MIO[53:48]
GPIOOutputMask, RW, u32); GPIOOutputMask, RW, u32);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_at!(GPIOOutputMask, 0xE000A00C, new); register_at!(GPIOOutputMask, 0xE000A00C, new);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_bit!(gpio_output_mask, register_bit!(gpio_output_mask,
/// Output for SCL /// Output for SCL
scl_o, 2); scl_o, 2);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_bit!(gpio_output_mask, register_bit!(gpio_output_mask,
/// Output for SDA /// Output for SDA
sda_o, 3); sda_o, 3);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_bits!(gpio_output_mask, register_bits!(gpio_output_mask,
/// Mask for keeping bits except SCL and SDA unchanged /// Mask for keeping bits except SCL and SDA unchanged
mask, u16, 16, 31); mask, u16, 16, 31);
@ -82,13 +83,13 @@ register!(gpio_input,
/// DATA_1_RO: /// DATA_1_RO:
/// Input data for MIO[53:32] /// Input data for MIO[53:32]
GPIOInput, RO, u32); GPIOInput, RO, u32);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_at!(GPIOInput, 0xE000A064, new); register_at!(GPIOInput, 0xE000A064, new);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_bit!(gpio_input, register_bit!(gpio_input,
/// Input for SCL /// Input for SCL
scl, 18); scl, 18);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_bit!(gpio_input, register_bit!(gpio_input,
/// Input for SDA /// Input for SDA
sda, 19); sda, 19);
@ -98,13 +99,13 @@ register!(gpio_direction,
/// DIRM_1: /// DIRM_1:
/// Direction mode for MIO[53:32]; 0/1 = in/out /// Direction mode for MIO[53:32]; 0/1 = in/out
GPIODirection, RW, u32); GPIODirection, RW, u32);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_at!(GPIODirection, 0xE000A244, new); register_at!(GPIODirection, 0xE000A244, new);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_bit!(gpio_direction, register_bit!(gpio_direction,
/// Direction for SCL /// Direction for SCL
scl, 18); scl, 18);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_bit!(gpio_direction, register_bit!(gpio_direction,
/// Direction for SDA /// Direction for SDA
sda, 19); sda, 19);
@ -117,13 +118,13 @@ register!(gpio_output_enable,
/// OEN_1: /// OEN_1:
/// Output enable for MIO[53:32] /// Output enable for MIO[53:32]
GPIOOutputEnable, RW, u32); GPIOOutputEnable, RW, u32);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_at!(GPIOOutputEnable, 0xE000A248, new); register_at!(GPIOOutputEnable, 0xE000A248, new);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_bit!(gpio_output_enable, register_bit!(gpio_output_enable,
/// Output enable for SCL /// Output enable for SCL
scl, 18); scl, 18);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
register_bit!(gpio_output_enable, register_bit!(gpio_output_enable,
/// Output enable for SDA /// Output enable for SDA
sda, 19); sda, 19);

2
libboard_zynq/src/lib.rs
View File

@ -19,7 +19,7 @@ pub mod gic;
pub mod time; pub mod time;
pub mod timer; pub mod timer;
pub mod sdio; pub mod sdio;
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
pub mod i2c; pub mod i2c;
pub mod logger; pub mod logger;
pub mod ps7_init; pub mod ps7_init;

18
libboard_zynq/src/sdio/mod.rs
View File

@ -116,8 +116,8 @@ impl Sdio {
.speed(true), .speed(true),
); );
} }
// redpitaya card detect pin // kasli_soc and redpitaya card detect pin
#[cfg(any(feature = "target_redpitaya", feature = "target_kasli_soc"))] #[cfg(any(feature = "target_kasli_soc", feature = "target_redpitaya"))]
{ {
unsafe { unsafe {
slcr.sd0_wp_cd_sel.write(46 << 16); slcr.sd0_wp_cd_sel.write(46 << 16);
@ -128,6 +128,20 @@ impl Sdio {
.speed(true), .speed(true),
); );
} }
// ebaz4205 card detect pin
#[cfg(feature = "target_ebaz4205")]
{
unsafe {
slcr.sd0_wp_cd_sel.write(34 << 16);
}
slcr.mio_pin_34.write(
slcr::MioPin34::zeroed()
.io_type(slcr::IoBufferType::Lvcmos33)
.pullup(true)
.speed(true),
);
}
slcr.sdio_rst_ctrl.reset_sdio0(); slcr.sdio_rst_ctrl.reset_sdio0();
slcr.aper_clk_ctrl.enable_sdio0(); slcr.aper_clk_ctrl.enable_sdio0();
slcr.sdio_clk_ctrl.enable_sdio0(); slcr.sdio_clk_ctrl.enable_sdio0();

8
libboard_zynq/src/slcr.rs
View File

@ -9,9 +9,11 @@ use libregister::{
#[repr(u8)] #[repr(u8)]
pub enum PllSource { pub enum PllSource {
IoPll = 0b00, IoPll = 0b000,
ArmPll = 0b10, ArmPll = 0b010,
DdrPll = 0b11, DdrPll = 0b011,
// Ethernet controller 0 EMIO clock
Emio = 0b100,
} }
#[repr(u8)] #[repr(u8)]

6
libboard_zynq/src/stdio.rs
View File

@ -47,7 +47,11 @@ impl DerefMut for LazyUart {
LazyUart::Uninitialized => { LazyUart::Uninitialized => {
#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))] #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
let uart = Uart::uart0(UART_RATE); let uart = Uart::uart0(UART_RATE);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] #[cfg(any(
feature = "target_zc706",
feature = "target_ebaz4205",
feature = "target_kasli_soc",
))]
let uart = Uart::uart1(UART_RATE); let uart = Uart::uart1(UART_RATE);
*self = LazyUart::Initialized(uart); *self = LazyUart::Initialized(uart);
self self

33
libboard_zynq/src/uart/mod.rs
View File

@ -79,6 +79,39 @@ impl Uart {
self_ self_
} }
#[cfg(feature = "target_ebaz4205")]
pub fn uart1(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| {
// Route UART 1 RxD/TxD Signals to MIO Pins
// TX pin
slcr.mio_pin_24.write(
slcr::MioPin24::zeroed()
.l3_sel(0b111)
.io_type(slcr::IoBufferType::Lvcmos33)
.pullup(true)
);
// RX pin
slcr.mio_pin_25.write(
slcr::MioPin25::zeroed()
.tri_enable(true)
.l3_sel(0b111)
.io_type(slcr::IoBufferType::Lvcmos33)
.pullup(true)
);
});
slcr::RegisterBlock::unlocked(|slcr| {
slcr.uart_rst_ctrl.reset_uart1();
slcr.aper_clk_ctrl.enable_uart1();
slcr.uart_clk_ctrl.enable_uart1();
});
let mut self_ = Uart {
regs: regs::RegisterBlock::uart1(),
};
self_.configure(baudrate);
self_
}
pub fn write_byte(&mut self, value: u8) { pub fn write_byte(&mut self, value: u8) {
while self.tx_fifo_full() {} while self.tx_fifo_full() {}

1
libconfig/Cargo.toml
View File

@ -13,6 +13,7 @@ log = "0.4"
[features] [features]
target_zc706 = [] target_zc706 = []
target_coraz7 = [] target_coraz7 = []
target_ebaz4205 = []
target_redpitaya = [] target_redpitaya = []
target_kasli_soc = [] target_kasli_soc = []
ipv6 = [] ipv6 = []

4
libconfig/src/net_settings.rs
View File

@ -59,6 +59,10 @@ pub fn get_addresses(cfg: &Config) -> NetAddresses {
let mut hardware_addr = get_address_from_eeprom(); let mut hardware_addr = get_address_from_eeprom();
#[cfg(feature = "target_kasli_soc")] #[cfg(feature = "target_kasli_soc")]
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56); let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
#[cfg(feature = "target_ebaz4205")]
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x57]);
#[cfg(feature = "target_ebaz4205")]
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 57);
if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) { if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
hardware_addr = addr; hardware_addr = addr;

1
libsupport_zynq/Cargo.toml
View File

@ -8,6 +8,7 @@ edition = "2018"
[features] [features]
target_zc706 = ["libboard_zynq/target_zc706"] target_zc706 = ["libboard_zynq/target_zc706"]
target_coraz7 = ["libboard_zynq/target_coraz7"] target_coraz7 = ["libboard_zynq/target_coraz7"]
target_ebaz4205 = ["libboard_zynq/target_ebaz4205"]
target_redpitaya = ["libboard_zynq/target_redpitaya"] target_redpitaya = ["libboard_zynq/target_redpitaya"]
target_kasli_soc = ["libboard_zynq/target_kasli_soc"] target_kasli_soc = ["libboard_zynq/target_kasli_soc"]
panic_handler = [] panic_handler = []

33
openocd/ebaz4205.cfg Normal file
View File

@ -0,0 +1,33 @@
# The contents of this file are partially dependend on
# the adapter that you have. Please modify accordingly.
adapter driver ftdi
ftdi vid_pid 0x0403 0x6010
ftdi channel 0
# Every pin set as high impedance except TCK, TDI, TDO and TMS
ftdi layout_init 0x0088 0x008b
# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
# This choice is arbitrary. Use other GPIO pin if desired.
ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
transport select jtag
adapter speed 10000
set PL_TAPID 0x13722093
set SMP 1
source ./zynq-7000.cfg
reset_config srst_only srst_open_drain
adapter srst pulse_width 250
adapter srst delay 400
source ./common.cfg
reset halt
# Disable MMU
targets $_TARGETNAME_1
arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]
targets $_TARGETNAME_0
arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]

1
szl/Cargo.toml
View File

@ -8,6 +8,7 @@ edition = "2018"
[features] [features]
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"] target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"] target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205"]
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"] target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"] target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
default = ["target_zc706"] default = ["target_zc706"]

5
szl/src/main.rs
View File

@ -80,12 +80,15 @@ pub fn main_core0() {
); );
info!("Simple Zynq Loader starting..."); info!("Simple Zynq Loader starting...");
#[cfg(not(feature = "target_kasli_soc"))] #[cfg(not(any(feature = "target_kasli_soc", feature = "target_ebaz4205")))]
const CPU_FREQ: u32 = 800_000_000; const CPU_FREQ: u32 = 800_000_000;
#[cfg(feature = "target_kasli_soc")] #[cfg(feature = "target_kasli_soc")]
const CPU_FREQ: u32 = 1_000_000_000; const CPU_FREQ: u32 = 1_000_000_000;
#[cfg(feature = "target_ebaz4205")]
const CPU_FREQ: u32 = 666_666_666;
ArmPll::setup(2 * CPU_FREQ); ArmPll::setup(2 * CPU_FREQ);
Clocks::set_cpu_freq(CPU_FREQ); Clocks::set_cpu_freq(CPU_FREQ);
IoPll::setup(1_000_000_000); IoPll::setup(1_000_000_000);