|
|
ef6d0ff3f1
|
boot: reset core1 before start
|
2019-11-18 00:38:03 +01:00 |
|
|
|
0bc941d789
|
main: start_core1
|
2019-11-16 00:53:30 +01:00 |
|
|
|
a416f48af1
|
main: add empty main_core1()
|
2019-11-16 00:21:57 +01:00 |
|
|
|
b6596d930d
|
boot: ACTLR.enable_smp()
|
2019-11-16 00:12:58 +01:00 |
|
|
|
49901d1b8a
|
boot: prepare core1 bootup
|
2019-11-15 23:59:01 +01:00 |
|
Björn Stein
|
4a1d0fc0c3
|
zynq::mpcore: add register definitions
|
2019-11-14 02:11:58 +01:00 |
|
|
|
50481b3a80
|
main: rm obsolete compile feature
|
2019-11-13 23:33:11 +01:00 |
|
|
|
b76dc4037d
|
main: change IP address to 192.168.1.51/24
|
2019-11-13 16:02:56 +01:00 |
|
|
|
caa69fda2e
|
main: refactor into boot
|
2019-11-11 02:46:18 +01:00 |
|
|
|
3279aab961
|
main: refactor into abort, panic, ram
|
2019-11-11 02:46:18 +01:00 |
|
|
|
92c274348f
|
zynq::eth: enable checksum offload
|
2019-11-11 01:42:41 +01:00 |
|
|
|
3eb7fce572
|
delint
|
2019-11-11 01:42:38 +01:00 |
|
|
|
b1472096ba
|
main: change IP address to 192.168.1.28/24
|
2019-11-11 01:40:07 +01:00 |
|
|
|
cb1b5776cd
|
Cargo.lock: update dependencies
|
2019-11-11 00:45:59 +01:00 |
|
|
|
3496755406
|
update rust + smoltcp
|
2019-11-11 00:28:46 +01:00 |
|
|
|
959bf8a245
|
zynq::eth: don't check_link_change if link already established
|
2019-11-11 00:08:48 +01:00 |
|
|
|
4d3b2ac7e5
|
zynq::ddr: use different data_bus_width for targets
DDR still works only on the zc706, not on the cora z7-10.
|
2019-11-11 00:06:35 +01:00 |
|
|
|
cae02947bc
|
zynq::eth: remove all memory barriers
They were not the solution.
|
2019-11-10 23:52:55 +01:00 |
|
|
|
afd96bd887
|
zynq::clocks: unlock slcr in enable_io()
|
2019-11-07 00:13:50 +01:00 |
|
|
|
261455877d
|
zynq::ddr: fix DDR 3x/2x setup, print clocks
|
2019-11-07 00:13:50 +01:00 |
|
|
|
ff96bf903b
|
zynq::ddr: only enable_ddr if no clock yet
that's only an issue for the cora z7
|
2019-11-07 00:13:50 +01:00 |
|
|
|
d2df5652d0
|
Revert "zynq: replace unnecessary slcr::unlocked with new"
This reverts commit 6bee1f44f4.
|
2019-11-07 00:13:50 +01:00 |
|
|
|
eb56dda44f
|
zynq::slcr::unlocked: fix comment
|
2019-11-07 00:13:50 +01:00 |
|
|
|
6e50b32e80
|
openocd: configure SRST for digilent_jtag_smt2_nc + Zynq
Digilent docs say Zynq boards should connect it to GPIO2.
Closes #2
|
2019-11-05 12:36:07 +08:00 |
|
|
|
74c43b3477
|
zynq::eth::tx: clear entry.word1 for each packet
|
2019-11-04 02:31:40 +01:00 |
|
|
|
99a00e019b
|
zynq::eth: implement phy::extended_status, set clock for link speed
|
2019-11-04 02:30:00 +01:00 |
|
|
|
961e2e1dd0
|
zynq::{ddr, eth}: fix clock divisor calculation
off-by-one, didn't change behavior.
|
2019-11-03 02:23:16 +01:00 |
|
|
|
04e816d99e
|
zynq::slcr: fix a bitfield index
that didn't solve our problems.
|
2019-11-03 02:01:42 +01:00 |
|
|
|
6bee1f44f4
|
zynq: replace unnecessary slcr::unlocked with new
|
2019-10-31 20:48:07 +01:00 |
|
|
|
54e4b9281f
|
main: rewrap linked_list_allocator
|
2019-10-31 19:21:02 +01:00 |
|
|
|
f688eb83ab
|
default.nix: update cargoSha256
|
2019-10-31 03:19:39 +01:00 |
|
|
|
5c62716a99
|
zynq::eth: switch rx and tx descriptor words to vcell
vcell can be initialized cleanly.
|
2019-10-31 03:15:13 +01:00 |
|
|
|
1f728686ff
|
rm ram, add linked_list_allocator on ddr
|
2019-10-31 01:41:10 +01:00 |
|
|
|
e248d3d3b1
|
zynq::ddr: optimize memtest
|
2019-10-31 01:32:45 +01:00 |
|
|
|
91bab76ab6
|
zynq::ddr: fix usable ram size
|
2019-10-31 01:27:49 +01:00 |
|
|
|
43501003f9
|
openocd/zc706: decimate adapter_khz for reliability
|
2019-10-31 00:28:19 +01:00 |
|
|
|
ceeaa6427e
|
zynq::ddr: fix typo
|
2019-10-28 23:58:25 +01:00 |
|
|
|
7cdf6c0918
|
start implementation of a StaticAllocator
|
2019-10-28 00:43:57 +01:00 |
|
|
|
fc39885d3b
|
zynq::ddr: fix clock setup
|
2019-10-28 00:43:09 +01:00 |
|
|
|
f199ac68b4
|
zynq::ddr: don't overwrite slcr.ddr_pll_ctrl
|
2019-10-27 22:54:34 +01:00 |
|
|
|
637bb35f43
|
zynq::ddr: fix memtest progress calculation
|
2019-10-27 20:38:35 +01:00 |
|
|
|
85bd506132
|
zynq::ddr: parameters
|
2019-10-27 20:38:06 +01:00 |
|
|
|
27114aec62
|
zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage
this seems to make DDR RAM work.
|
2019-10-27 20:30:56 +01:00 |
|
|
|
9b4f07f37c
|
zynq::ddr, main: parameters, memtest
|
2019-10-25 23:19:34 +02:00 |
|
|
|
e61d1268ac
|
zynq::slcr: doc, fix
|
2019-10-25 23:18:18 +02:00 |
|
|
|
a4d3360a70
|
zynq::slcr: implement Display for PllStatus
|
2019-10-25 20:38:10 +02:00 |
|
|
|
838434cdec
|
zynq::ddr: wait for init
|
2019-10-25 19:15:22 +02:00 |
|
|
|
4cf5283ba8
|
zynq::ddr: implement reset_ddrc(), add to main
|
2019-10-24 01:39:14 +02:00 |
|
|
|
a8886de067
|
zynq::ddr: implement configure_iob()
|
2019-10-24 01:24:12 +02:00 |
|
|
|
afda48e3fe
|
zynq::ddr: add clock_setup(), calibrate_iob_impedance()
|
2019-10-22 01:25:35 +02:00 |
|
