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8a9dde6119
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zynq::flash: add consts
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2019-12-14 01:57:51 +01:00 |
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5268839467
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zynq::flash: add write_enabled()
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2019-12-14 01:56:49 +01:00 |
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0b9a150255
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zynq::flash: abstract SpiFlashRegister
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2019-12-14 01:55:17 +01:00 |
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2d1c8e1f4f
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zynq::flash: fix txd[123] alignment
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2019-12-14 01:07:15 +01:00 |
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e1068af948
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zynq::flash: add rdsr1()
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2019-12-12 01:02:09 +01:00 |
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3b3b5dc7c1
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zynq::flash: add support for writing 1/2/3-byte words
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2019-12-12 00:17:34 +01:00 |
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70d56d2b28
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zynq::flash: doc
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2019-12-12 00:13:02 +01:00 |
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b346ea8297
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zynq::flash: fix INST_RDCR
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2019-12-12 00:11:42 +01:00 |
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e9b80eaef9
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zynq::flash: don't send excess data, fixes, refactorings
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2019-12-10 02:50:44 +01:00 |
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0823a74164
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zynq::flash: fix rx_thres register
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2019-12-10 02:46:25 +01:00 |
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aab82f6843
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zynq::flash: enable big endian mode
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2019-12-10 02:45:05 +01:00 |
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f3676c945a
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zynq::flash: flush after instruction
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2019-12-07 02:48:55 +01:00 |
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1e465250f5
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zynq::flash: enable/disable spi for every transfer
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2019-12-07 02:11:50 +01:00 |
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e37659e4b3
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zynq::flash: refactor
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2019-12-05 01:18:52 +01:00 |
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45cc271735
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zynq::flash: fix + refactor
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2019-12-05 00:05:34 +01:00 |
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cfaa1213e2
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zynq::flash: add more initialization
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2019-12-03 02:41:49 +01:00 |
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7107244a6e
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zynq::flash: start implementing Manual mode
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2019-11-30 02:48:39 +01:00 |
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dd3ad3be67
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zynq::flash: implement stopping LinearAddressing mode
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2019-11-29 23:48:08 +01:00 |
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a8a7f11990
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zynq::flash: configure quad i/o fast read mode
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2019-11-29 23:37:54 +01:00 |
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78caca1f04
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zynq::flash: setup additional signals
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2019-11-28 03:22:26 +01:00 |
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5642feb824
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zynq::flash: add missing config bits to enable addressing mode
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2019-11-28 03:02:51 +01:00 |
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a199a5dc7d
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zynq::flash: add more setup
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2019-11-23 01:59:24 +01:00 |
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3180f1c3f7
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zynq::flash: begin driver implementation
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2019-11-21 00:14:09 +01:00 |
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