|
1e465250f5
|
zynq::flash: enable/disable spi for every transfer
|
2019-12-07 02:11:50 +01:00 |
|
|
e37659e4b3
|
zynq::flash: refactor
|
2019-12-05 01:18:52 +01:00 |
|
|
45cc271735
|
zynq::flash: fix + refactor
|
2019-12-05 00:05:34 +01:00 |
|
|
cfaa1213e2
|
zynq::flash: add more initialization
|
2019-12-03 02:41:49 +01:00 |
|
|
7107244a6e
|
zynq::flash: start implementing Manual mode
|
2019-11-30 02:48:39 +01:00 |
|
|
dd3ad3be67
|
zynq::flash: implement stopping LinearAddressing mode
|
2019-11-29 23:48:08 +01:00 |
|
|
a8a7f11990
|
zynq::flash: configure quad i/o fast read mode
|
2019-11-29 23:37:54 +01:00 |
|
|
78caca1f04
|
zynq::flash: setup additional signals
|
2019-11-28 03:22:26 +01:00 |
|
|
5642feb824
|
zynq::flash: add missing config bits to enable addressing mode
|
2019-11-28 03:02:51 +01:00 |
|
|
a199a5dc7d
|
zynq::flash: add more setup
|
2019-11-23 01:59:24 +01:00 |
|
|
3180f1c3f7
|
zynq::flash: begin driver implementation
|
2019-11-21 00:14:09 +01:00 |
|