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zynq-rs
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openocd: adapt to newer version

This commit is contained in:
Sebastien Bourdeauducq 2021-06-25 17:01:02 +08:00
parent 104d1ef232
commit c7e9f85de2
5 changed files with 10 additions and 9 deletions
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2
openocd/digilent-hs2.cfg
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@ -3,7 +3,7 @@
# this supports JTAG-HS2 (and apparently Nexys4 as well) # this supports JTAG-HS2 (and apparently Nexys4 as well)
interface ftdi adapter driver ftdi
ftdi_vid_pid 0x0403 0x6014 ftdi_vid_pid 0x0403 0x6014
ftdi_channel 0 ftdi_channel 0

8
openocd/kasli_soc.cfg
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@ -1,11 +1,11 @@
interface ftdi adapter driver ftdi
ftdi_device_desc "Quad RS232-HS" ftdi_device_desc "Quad RS232-HS"
ftdi_vid_pid 0x0403 0x6011 ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0 ftdi_channel 0
# some GPIOs need to be set, otherwise the FTDI chip craps out for some reason. # some GPIOs need to be set, otherwise the FTDI chip craps out for some reason.
ftdi_layout_init 0x0098 0x008b ftdi_layout_init 0x0098 0x008b
transport select jtag transport select jtag
adapter_khz 1000 adapter speed 1000
set PL_TAPID 0x1372c093 set PL_TAPID 0x1372c093
set SMP 1 set SMP 1
@ -14,8 +14,8 @@ source ./zynq-7000.cfg
ftdi_layout_signal nSRST -oe 0x0004 ftdi_layout_signal nSRST -oe 0x0004
reset_config srst_only srst_open_drain reset_config srst_only srst_open_drain
adapter_nsrst_assert_width 250 adapter srst pulse_width 250
adapter_nsrst_delay 400 adapter srst delay 400
set XC7_JSHUTDOWN 0x0d set XC7_JSHUTDOWN 0x0d
set XC7_JPROGRAM 0x0b set XC7_JPROGRAM 0x0b

2
openocd/redpitaya.cfg
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@ -1,5 +1,5 @@
source ./digilent-hs2.cfg source ./digilent-hs2.cfg
adapter_khz 1000 adapter speed 1000
set PL_TAPID 0x13722093 set PL_TAPID 0x13722093
set SMP 1 set SMP 1

2
openocd/zc706.cfg
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@ -1,5 +1,5 @@
source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
adapter_khz 1000 adapter speed 1000
set PL_TAPID 0x23731093 set PL_TAPID 0x23731093
set SMP 1 set SMP 1

5
openocd/zynq-7000.cfg
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@ -81,15 +81,16 @@ jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \
set _TARGETNAME_0 $_CHIPNAME.cpu.0 set _TARGETNAME_0 $_CHIPNAME.cpu.0
set _TARGETNAME_1 $_CHIPNAME.cpu.1 set _TARGETNAME_1 $_CHIPNAME.cpu.1
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
target create $_TARGETNAME_0 cortex_a -coreid 0 \ target create $_TARGETNAME_0 cortex_a -coreid 0 \
-endian $_ENDIAN \ -endian $_ENDIAN \
-chain-position $_CHIPNAME.dap \ -dap $_CHIPNAME.dap \
-dbgbase 0x80090000 -dbgbase 0x80090000
if { $_SMP } { if { $_SMP } {
echo "Zynq CPU1." echo "Zynq CPU1."
target create $_TARGETNAME_1 cortex_a -coreid 1 \ target create $_TARGETNAME_1 cortex_a -coreid 1 \
-endian $_ENDIAN \ -endian $_ENDIAN \
-chain-position $_CHIPNAME.dap \ -dap $_CHIPNAME.dap \
-dbgbase 0x80092000 -dbgbase 0x80092000
target smp $_TARGETNAME_0 $_TARGETNAME_1 target smp $_TARGETNAME_0 $_TARGETNAME_1
} }