forked from M-Labs/zynq-rs
slcr: init gem* rclk/clk
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@ -119,6 +119,20 @@ impl Eth {
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}
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pub fn gem0() -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Enable gem0 ref clock
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slcr.gem0_rclk_ctrl.write(
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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slcr.gem0_clk_ctrl.write(
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slcr::ClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(10)
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);
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});
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let regs = regs::RegisterBlock::gem0();
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Eth { regs }.init()
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}
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26
src/slcr.rs
26
src/slcr.rs
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@ -33,10 +33,10 @@ pub struct RegisterBlock {
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pub aper_clk_ctrl: AperClkCtrl,
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pub usb0_clk_ctrl: RW<u32>,
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pub usb1_clk_ctrl: RW<u32>,
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pub gem0_rclk_ctrl: RW<u32>,
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pub gem1_rclk_ctrl: RW<u32>,
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pub gem0_clk_ctrl: RW<u32>,
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pub gem1_clk_ctrl: RW<u32>,
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pub gem0_rclk_ctrl: RclkCtrl,
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pub gem1_rclk_ctrl: RclkCtrl,
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pub gem0_clk_ctrl: ClkCtrl,
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pub gem1_clk_ctrl: ClkCtrl,
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pub smc_clk_ctrl: RW<u32>,
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pub lqspi_clk_ctrl: RW<u32>,
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pub sdio_clk_ctrl: RW<u32>,
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@ -254,6 +254,24 @@ impl AperClkCtrl {
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}
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}
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register!(rclk_ctrl, RclkCtrl, RW, u32);
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register_bit!(rclk_ctrl,
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/// Ethernet controller Rx clock control
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clkact, 0);
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register_bit!(rclk_ctrl,
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/// false: MIO, true: EMIO
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srcsel, 4);
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register!(clk_ctrl, ClkCtrl, RW, u32);
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register_bits!(clk_ctrl,
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/// Divisor for source clock
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divisor, u8, 8, 13);
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register_bits_typed!(clk_ctrl,
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/// Source to generate the ref clock
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srcsel, u8, PllSource, 4, 5);
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register_bit!(clk_ctrl,
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/// SMC reference clock control
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clkact, 0);
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register!(uart_clk_ctrl, UartClkCtrl, RW, u32);
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register_bit!(uart_clk_ctrl, clkact0, 0);
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