forked from M-Labs/zynq-rs
eth: doc
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@ -81,6 +81,8 @@ impl DescList {
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entry.word1.write(
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entry.word1.write(
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DescWord1::zeroed()
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DescWord1::zeroed()
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);
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);
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// Flush buffer from cache, to be filled by the peripheral
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// before next read
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dcci_slice(&buffer[..]);
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dcci_slice(&buffer[..]);
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}
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}
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@ -129,6 +131,8 @@ pub struct PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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fn drop(&mut self) {
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fn drop(&mut self) {
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// Flush buffer from cache, to be filled by the peripheral
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// before next read
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dcci_slice(self.buffer);
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dcci_slice(self.buffer);
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self.entry.word0.modify(|_, w| w.used(false));
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self.entry.word0.modify(|_, w| w.used(false));
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@ -124,12 +124,13 @@ pub struct PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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impl<'a> Drop for PktRef<'a> {
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fn drop(&mut self) {
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fn drop(&mut self) {
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// Write back all dirty cachelines of this buffer
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dcc_slice(self.buffer);
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dcc_slice(self.buffer);
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self.entry.word1.modify(|_, w| w.used(false));
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self.entry.word1.modify(|_, w| w.used(false));
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if ! self.regs.tx_status.read().tx_go() {
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if ! self.regs.tx_status.read().tx_go() {
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self.regs.net_ctrl.modify(|_, w|
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// Start TX if not already running
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w.start_tx(true)
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self.regs.net_ctrl.modify(|_, w| w.start_tx(true));
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);
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}
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}
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}
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}
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}
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}
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