forked from M-Labs/zynq-rs
more cpu options
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66c66447dd
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@ -154,7 +154,7 @@ register_bit!(scu_control, enable, 0);
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impl ScuControl {
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impl ScuControl {
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pub fn start(&mut self) {
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pub fn start(&mut self) {
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self.modify(|_, w| w.enable(true));
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self.modify(|_, w| w.enable(true).scu_speculative_linefill_enable(true));
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}
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}
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}
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}
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@ -158,7 +158,7 @@ impl L1Table {
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global: true,
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global: true,
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shareable: true,
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shareable: true,
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access: AccessPermissions::FullAccess,
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access: AccessPermissions::FullAccess,
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tex: 0b101,
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tex: 0b0,
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domain: 0b1111,
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domain: 0b1111,
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exec: true,
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exec: true,
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cacheable: true,
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cacheable: true,
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@ -213,7 +213,7 @@ impl L1Table {
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access: AccessPermissions::FullAccess,
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access: AccessPermissions::FullAccess,
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tex: 0,
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tex: 0,
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domain: 0,
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domain: 0,
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exec: true,
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exec: false,
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cacheable: false,
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cacheable: false,
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bufferable: true,
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bufferable: true,
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});
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});
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