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zynq-rs
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regs: properly emit doc_comments

This commit is contained in:
Astro 2019-05-24 23:49:49 +02:00
parent 56c2f1d833
commit 6bf210366a
4 changed files with 151 additions and 95 deletions
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149
src/eth/regs.rs
View File

@ -127,61 +127,87 @@ register!(net_ctrl, NetCtrl, RW, u32);
register_bit!(net_ctrl, clear_stat_regs, 5); register_bit!(net_ctrl, clear_stat_regs, 5);
register!(net_cfg, NetCfg, RW, u32); register!(net_cfg, NetCfg, RW, u32);
/// false for 10Mbps, true for 100Mbps register_bit!(net_cfg,
register_bit!(net_cfg, speed, 0); /// false for 10Mbps, true for 100Mbps
speed, 0);
register_bit!(net_cfg, full_duplex, 1); register_bit!(net_cfg, full_duplex, 1);
/// Discard non-VLAN frames register_bit!(net_cfg,
register_bit!(net_cfg, disc_non_vlan, 2); /// Discard non-VLAN frames
/// Accept all valid frames? disc_non_vlan, 2);
register_bit!(net_cfg, copy_all, 4); register_bit!(net_cfg,
/// Don't accept broadcast destination address /// Accept all valid frames?
register_bit!(net_cfg, no_broadcast, 5); copy_all, 4);
/// Multicast hash enable register_bit!(net_cfg,
register_bit!(net_cfg, multi_hash_en, 6); /// Don't accept broadcast destination address
/// Unicast hash enable no_broadcast, 5);
register_bit!(net_cfg, uni_hash_en, 7); register_bit!(net_cfg,
/// Accept frames up to 1536 bytes (instead of up to 1518 bytes) /// Multicast hash enable
register_bit!(net_cfg, rx_1536_byte_frames, 8); multi_hash_en, 6);
/// External address match enable - when set the external address register_bit!(net_cfg,
/// match interface can be used to copy frames to memory. /// Unicast hash enable
register_bit!(net_cfg, ext_addr_match_en, 9); uni_hash_en, 7);
/// Gigabit mode enable register_bit!(net_cfg,
register_bit!(net_cfg, gige_en, 10); /// Accept frames up to 1536 bytes (instead of up to 1518 bytes)
/// Enable TBI instead of GMII/MII interface? rx_1536_byte_frames, 8);
register_bit!(net_cfg, pcs_sel, 11); register_bit!(net_cfg,
/// Retry test (reduces backoff between collisions to one slot) /// match interface can be used to copy frames to memory.
register_bit!(net_cfg, retry_test, 12); /// External address match enable - when set the external address
/// Pause frame enable ext_addr_match_en, 9);
register_bit!(net_cfg, pause_en, 13); register_bit!(net_cfg,
/// Receive buffer offset /// Gigabit mode enable
register_bits!(net_cfg, rx_buf_offset, u8, 14, 15); gige_en, 10);
/// Length field error frame discard register_bit!(net_cfg,
register_bit!(net_cfg, len_err_frame_disc, 16); /// Enable TBI instead of GMII/MII interface?
/// Write received frames to memory with Frame Check Sequence removed pcs_sel, 11);
register_bit!(net_cfg, fcs_remove, 17); register_bit!(net_cfg,
/// MDC clock divison /// Retry test (reduces backoff between collisions to one slot)
register_bits!(net_cfg, mdc_clk_div, u8, 18, 20); retry_test, 12);
/// Data bus width register_bit!(net_cfg,
register_bits!(net_cfg, dbus_width, u8, 21, 22); /// Pause frame enable
/// Disable copy of pause frames pause_en, 13);
register_bit!(net_cfg, dis_cp_pause_frame, 23); register_bits!(net_cfg,
/// Receive checksum offload enable /// Receive buffer offset
register_bit!(net_cfg, rx_chksum_offld_en, 24); rx_buf_offset, u8, 14, 15);
/// Enable frames to be received in half-duplex mode while register_bit!(net_cfg,
/// transmitting /// Length field error frame discard
register_bit!(net_cfg, rx_hd_while_tx, 25); len_err_frame_disc, 16);
/// Ignore Rx Framce Check Sequence (errors will not be rejected) register_bit!(net_cfg,
register_bit!(net_cfg, ignore_rx_fcs, 26); /// Write received frames to memory with Frame Check Sequence removed
/// SGMII mode enable fcs_remove, 17);
register_bit!(net_cfg, sgmii_en, 27); register_bits!(net_cfg,
/// IPG stretch enable /// MDC clock divison
register_bit!(net_cfg, ipg_stretch_en, 28); mdc_clk_div, u8, 18, 20);
/// Receive bad preamble register_bits!(net_cfg,
register_bit!(net_cfg, rx_bad_preamble, 29); /// Data bus width
/// Ignore IPG rx_er dbus_width, u8, 21, 22);
register_bit!(net_cfg, ignore_ipg_rx_er, 30); register_bit!(net_cfg,
/// NA /// Disable copy of pause frames
register_bit!(net_cfg, unidir_en, 31); dis_cp_pause_frame, 23);
register_bit!(net_cfg,
/// Receive checksum offload enable
rx_chksum_offld_en, 24);
register_bit!(net_cfg,
/// Enable frames to be received in half-duplex mode while
/// transmitting
rx_hd_while_tx, 25);
register_bit!(net_cfg,
/// Ignore Rx Framce Check Sequence (errors will not be rejected)
ignore_rx_fcs, 26);
register_bit!(net_cfg,
/// SGMII mode enable
sgmii_en, 27);
register_bit!(net_cfg,
/// IPG stretch enable
ipg_stretch_en, 28);
register_bit!(net_cfg,
/// Receive bad preamble
rx_bad_preamble, 29);
register_bit!(net_cfg,
/// Ignore IPG rx_er
ignore_ipg_rx_er, 30);
register_bit!(net_cfg,
/// NA
unidir_en, 31);
register!(net_status, NetStatus, RW, u32); register!(net_status, NetStatus, RW, u32);
register_bit!(net_status, pcs_link_state, 0); register_bit!(net_status, pcs_link_state, 0);
@ -250,14 +276,17 @@ pub enum PhyOperation {
} }
register!(phy_maint, PhyMaint, RW, u32); register!(phy_maint, PhyMaint, RW, u32);
/// Read from/write to the PHY register_bits!(phy_maint,
register_bits!(phy_maint, data, u16, 0, 15); /// Read from/write to the PHY
data, u16, 0, 15);
// Write `0b10` // Write `0b10`
register_bits!(phy_maint, must_10, u8, 16, 17); register_bits!(phy_maint, must_10, u8, 16, 17);
/// Register address register_bits!(phy_maint,
register_bits!(phy_maint, reg_addr, u8, 18, 22); /// Register address
/// PHY address reg_addr, u8, 18, 22);
register_bits!(phy_maint, phy_addr, u8, 23, 27); register_bits!(phy_maint,
/// PHY address
phy_addr, u8, 23, 27);
register_bits_typed!(phy_maint, operation, u8, PhyOperation, 28, 29); register_bits_typed!(phy_maint, operation, u8, PhyOperation, 28, 29);
// PHY clause 22 compliant (not clause 45)? // PHY clause 22 compliant (not clause 45)?
register_bit!(phy_maint, clause_22, 30); register_bit!(phy_maint, clause_22, 30);

20
src/regs.rs
View File

@ -121,8 +121,10 @@ macro_rules! register {
/// Define a 1-bit field of a register /// Define a 1-bit field of a register
#[macro_export] #[macro_export]
macro_rules! register_bit { macro_rules! register_bit {
($mod_name: ident, $name: ident, $bit: expr) => ( ($mod_name: ident, $(#[$outer:meta])* $name: ident, $bit: expr) => (
$(#[$outer])*
impl $mod_name::Read { impl $mod_name::Read {
#[allow(unused)]
pub fn $name(&self) -> bool { pub fn $name(&self) -> bool {
use bit_field::BitField; use bit_field::BitField;
@ -130,7 +132,9 @@ macro_rules! register_bit {
} }
} }
$(#[$outer])*
impl $mod_name::Write { impl $mod_name::Write {
#[allow(unused)]
pub fn $name(mut self, value: bool) -> Self { pub fn $name(mut self, value: bool) -> Self {
use bit_field::BitField; use bit_field::BitField;
@ -144,8 +148,10 @@ macro_rules! register_bit {
/// Define a multi-bit field of a register /// Define a multi-bit field of a register
#[macro_export] #[macro_export]
macro_rules! register_bits { macro_rules! register_bits {
($mod_name: ident, $name: ident, $type: ty, $bit_begin: expr, $bit_end: expr) => ( ($mod_name: ident, $(#[$outer:meta])* $name: ident, $type: ty, $bit_begin: expr, $bit_end: expr) => (
impl $mod_name::Read { impl $mod_name::Read {
#[allow(unused)]
$(#[$outer])*
pub fn $name(&self) -> $type { pub fn $name(&self) -> $type {
use bit_field::BitField; use bit_field::BitField;
@ -153,7 +159,10 @@ macro_rules! register_bits {
} }
} }
#[allow(unused)]
$(#[$outer])*
impl $mod_name::Write { impl $mod_name::Write {
#[allow(unused)]
pub fn $name(mut self, value: $type) -> Self { pub fn $name(mut self, value: $type) -> Self {
use bit_field::BitField; use bit_field::BitField;
@ -170,8 +179,10 @@ macro_rules! register_bits {
/// definition must be annotated with `#[repr($bit_type)]`! /// definition must be annotated with `#[repr($bit_type)]`!
#[macro_export] #[macro_export]
macro_rules! register_bits_typed { macro_rules! register_bits_typed {
($mod_name: ident, $name: ident, $bit_type: ty, $type: ty, $bit_begin: expr, $bit_end: expr) => ( ($mod_name: ident, $(#[$outer:meta])* $name: ident, $bit_type: ty, $type: ty, $bit_begin: expr, $bit_end: expr) => (
impl $mod_name::Read { impl $mod_name::Read {
#[allow(unused)]
$(#[$outer])*
pub fn $name(&self) -> $type { pub fn $name(&self) -> $type {
use bit_field::BitField; use bit_field::BitField;
@ -181,6 +192,8 @@ macro_rules! register_bits_typed {
} }
impl $mod_name::Write { impl $mod_name::Write {
#[allow(unused)]
$(#[$outer])*
pub fn $name(mut self, value: $type) -> Self { pub fn $name(mut self, value: $type) -> Self {
use bit_field::BitField; use bit_field::BitField;
@ -196,6 +209,7 @@ macro_rules! register_bits_typed {
macro_rules! register_at { macro_rules! register_at {
($name: ident, $addr: expr, $ctor: ident) => ( ($name: ident, $addr: expr, $ctor: ident) => (
impl $name { impl $name {
#[allow(unused)]
pub fn $ctor() -> &'static mut Self { pub fn $ctor() -> &'static mut Self {
let addr = $addr as *mut Self; let addr = $addr as *mut Self;
unsafe { &mut *addr } unsafe { &mut *addr }

2
src/uart/mod.rs
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@ -1,5 +1,3 @@
#![allow(unused)]
use core::fmt; use core::fmt;
use volatile_register::RW; use volatile_register::RW;

75
src/uart/regs.rs
View File

@ -62,41 +62,56 @@ register_bit!(control, sttbrk, 7);
register_bit!(control, stpbrk, 8); register_bit!(control, stpbrk, 8);
register!(mode, Mode, RW, u32); register!(mode, Mode, RW, u32);
/// Channel mode: Defines the mode of operation of the UART. register_bits_typed!(mode,
register_bits_typed!(mode, chmode, u8, ChannelMode, 8, 9); /// Channel mode: Defines the mode of operation of the UART.
/// Number of stop bits chmode, u8, ChannelMode, 8, 9);
register_bits_typed!(mode, nbstop, u8, StopBits, 6, 7); register_bits_typed!(mode,
/// Parity type select /// Number of stop bits
register_bits_typed!(mode, par, u8, ParityMode, 3, 5); nbstop, u8, StopBits, 6, 7);
/// Character length select register_bits_typed!(mode,
register_bits!(mode, chrl, u8, 1, 2); /// Parity type select
/// Clock source select par, u8, ParityMode, 3, 5);
register_bit!(mode, clks, 0); register_bits!(mode,
/// Character length select
chrl, u8, 1, 2);
register_bit!(mode,
/// Clock source select
clks, 0);
register!(baud_rate_gen, BaudRateGen, RW, u32); register!(baud_rate_gen, BaudRateGen, RW, u32);
register_bits!(baud_rate_gen, cd, u16, 0, 15); register_bits!(baud_rate_gen, cd, u16, 0, 15);
register!(channel_sts, ChannelSts, RO, u32); register!(channel_sts, ChannelSts, RO, u32);
/// Transmitter FIFO Nearly Full register_bit!(channel_sts,
register_bit!(channel_sts, tnful, 14); /// Transmitter FIFO Nearly Full
/// Tx FIFO fill level is greater than or equal to TTRIG? tnful, 14);
register_bit!(channel_sts, ttrig, 13); register_bit!(channel_sts,
/// Rx FIFO fill level is greater than or equal to FDEL? /// Tx FIFO fill level is greater than or equal to TTRIG?
register_bit!(channel_sts, flowdel, 12); ttrig, 13);
/// Transmitter state machine active? register_bit!(channel_sts,
register_bit!(channel_sts, tactive, 11); /// Rx FIFO fill level is greater than or equal to FDEL?
/// Receiver state machine active? flowdel, 12);
register_bit!(channel_sts, ractive, 10); register_bit!(channel_sts,
/// Tx FIFO is full? /// Transmitter state machine active?
register_bit!(channel_sts, txfull, 4); tactive, 11);
/// Tx FIFO is empty? register_bit!(channel_sts,
register_bit!(channel_sts, txempty, 3); /// Receiver state machine active?
/// Rx FIFO is full? ractive, 10);
register_bit!(channel_sts, rxfull, 2); register_bit!(channel_sts,
/// Rx FIFO is empty? /// Tx FIFO is full?
register_bit!(channel_sts, rxempty, 1); txfull, 4);
/// Rx FIFO fill level is greater than or equal to RTRIG? register_bit!(channel_sts,
register_bit!(channel_sts, rxovr, 0); /// Tx FIFO is empty?
txempty, 3);
register_bit!(channel_sts,
/// Rx FIFO is full?
rxfull, 2);
register_bit!(channel_sts,
/// Rx FIFO is empty?
rxempty, 1);
register_bit!(channel_sts,
/// Rx FIFO fill level is greater than or equal to RTRIG?
rxovr, 0);
register!(tx_rx_fifo, TxRxFifo, RW, u32); register!(tx_rx_fifo, TxRxFifo, RW, u32);
register_bits!(tx_rx_fifo, data, u32, 0, 31); register_bits!(tx_rx_fifo, data, u32, 0, 31);