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zynq-rs
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libboard_zynq: use Void in uart embedded_hal impl

This commit is contained in:
Astro 2020-04-25 00:28:17 +02:00
parent f835192c0a
commit 4ab6fb6271
3 changed files with 6 additions and 3 deletions
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1
Cargo.lock generated
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@ -66,6 +66,7 @@ dependencies = [
"libregister 0.0.0", "libregister 0.0.0",
"nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)", "nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
"smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)", "smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)",
"void 1.0.2 (registry+https://github.com/rust-lang/crates.io-index)",
"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)", "volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
] ]

1
libboard_zynq/Cargo.toml
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@ -14,6 +14,7 @@ volatile-register = "0.2"
bit_field = "0.10" bit_field = "0.10"
embedded-hal = "0.2" embedded-hal = "0.2"
nb = "0.1" nb = "0.1"
void = { version = "1", default-features = false }
libregister = { path = "../libregister" } libregister = { path = "../libregister" }
libcortex_a9 = { path = "../libcortex_a9" } libcortex_a9 = { path = "../libcortex_a9" }

7
libboard_zynq/src/uart/mod.rs
View File

@ -1,4 +1,5 @@
use core::fmt; use core::fmt;
use void::Void;
use libregister::*; use libregister::*;
use super::slcr; use super::slcr;
@ -209,9 +210,9 @@ impl fmt::Write for Uart {
/// embedded_hal async API /// embedded_hal async API
impl embedded_hal::serial::Write<u8> for Uart { impl embedded_hal::serial::Write<u8> for Uart {
type Error = (); type Error = Void;
fn write(&mut self, b: u8) -> nb::Result<(), ()> { fn write(&mut self, b: u8) -> nb::Result<(), Void> {
if self.tx_fifo_full() { if self.tx_fifo_full() {
Err(nb::Error::WouldBlock) Err(nb::Error::WouldBlock)
} else { } else {
@ -220,7 +221,7 @@ impl embedded_hal::serial::Write<u8> for Uart {
} }
} }
fn flush(&mut self) -> nb::Result<(), ()> { fn flush(&mut self) -> nb::Result<(), Void> {
if self.tx_fifo_empty() { if self.tx_fifo_empty() {
Ok(()) Ok(())
} else { } else {