forked from M-Labs/zynq-rs
uart: wait for reset
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47ec0116a9
commit
43b6d3acd0
20
src/slcr.rs
20
src/slcr.rs
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@ -96,12 +96,24 @@ register_bit!(uart_rst_ctrl, uart1_cpu1x_rst, 0);
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register_at!(UartRstCtrl, 0xF8000228, new);
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impl UartRstCtrl {
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pub fn reset_uart0(&self) {
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self.modify(|_, w| w.uart0_ref_rst(true));
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self.modify(|_, w| w.uart0_ref_rst(false));
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self.modify(|_, w|
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w.uart0_ref_rst(true)
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.uart0_cpu1x_rst(true)
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);
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self.modify(|_, w|
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w.uart0_ref_rst(false)
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.uart0_cpu1x_rst(false)
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);
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}
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pub fn reset_uart1(&self) {
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self.modify(|_, w| w.uart1_ref_rst(true));
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self.modify(|_, w| w.uart1_ref_rst(false));
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self.modify(|_, w|
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w.uart1_ref_rst(true)
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.uart1_cpu1x_rst(true)
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);
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self.modify(|_, w|
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w.uart1_ref_rst(false)
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.uart1_cpu1x_rst(false)
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);
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}
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}
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@ -7,14 +7,6 @@ use crate::regs::*;
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mod regs;
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#[repr(u8)]
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pub enum ParityMode {
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EvenParity = 0b000,
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OddParity = 0b001,
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ForceTo0 = 0b010,
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ForceTo1 = 0b011,
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}
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pub struct Uart {
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regs: &'static mut regs::RegisterBlock,
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}
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@ -63,24 +55,28 @@ impl Uart {
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// * 1 stop bit
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// * Normal channel mode
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// * no parity
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let parity_mode = ParityMode::ForceTo0;
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let parity_mode = regs::ParityMode::None;
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self.regs.mode.write(
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regs::Mode::zeroed()
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.par(parity_mode as u8)
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.chmode(regs::ChannelMode::AutomaticEcho as u8)
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.chmode(regs::ChannelMode::Normal as u8)
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);
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// Configure the Baud Rate
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self.disable_rx();
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self.disable_tx();
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// 115,200 baud
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self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(0x28B));
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self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(0xF));
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// 9,600 baud
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self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(651));
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self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(7));
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// // 115,200 baud
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// self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(62));
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// self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(6));
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// Enable controller
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self.reset_rx();
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self.reset_tx();
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self.wait_reset();
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self.enable_rx();
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self.enable_tx();
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@ -128,6 +124,15 @@ impl Uart {
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})
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}
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/// Wait for `reset_rx()` or `reset_tx()` to complete
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fn wait_reset(&self) {
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let mut pending = true;
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while pending {
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let control = self.regs.control.read();
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pending = control.rxrst() || control.txrst();
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}
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}
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fn set_break(&self, startbrk: bool, stopbrk: bool) {
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self.regs.control.modify(|_, w| {
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w.sttbrk(startbrk)
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@ -9,6 +9,15 @@ pub enum ChannelMode {
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RemoteLoopback = 0b11,
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}
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pub enum ParityMode {
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EvenParity = 0b000,
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OddParity = 0b001,
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ForceTo0 = 0b010,
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ForceTo1 = 0b011,
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None = 0b111,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub control: Control,
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