srenblad
/
zynq-rs
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Pull Requests Activity

libsupport_zynq/boot: fix cache mainteinance opertaions

This commit is contained in:
pca006132 2020-08-20 11:51:24 +08:00
parent 283bc9b810
commit 1ba0aa450f
1 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
libsupport_zynq/src/boot.rs
View File

@ -4,7 +4,7 @@ use libregister::{
VolatileCell, VolatileCell,
RegisterR, RegisterW, RegisterRW, RegisterR, RegisterW, RegisterRW,
}; };
use libcortex_a9::{asm, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock}; use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock};
use libboard_zynq::{slcr, mpcore}; use libboard_zynq::{slcr, mpcore};
extern "C" { extern "C" {
@ -101,7 +101,7 @@ fn l1_cache_init() {
// for all of the L1 data cache rather than a (previously // for all of the L1 data cache rather than a (previously
// unspecified) combination of one cache set and one cache // unspecified) combination of one cache set and one cache
// way. // way.
dciall(); dciall_l1();
} }
pub struct Core1 { pub struct Core1 {
@ -131,12 +131,13 @@ impl Core1 {
unsafe { unsafe {
CORE1_ENABLED.set(true); CORE1_ENABLED.set(true);
} }
// Ensure values have been written to cache
asm::dmb();
// Flush cache-line // Flush cache-line
cache::dccmvac(unsafe { &CORE1_ENABLED } as *const _ as usize); cache::dcc(unsafe { &CORE1_ENABLED });
if sdram { if sdram {
cache::dccmvac(0); cache::dccmvac(0);
asm::dsb();
l2c::l2_cache_clean(0);
l2c::l2_cache_sync();
} }
// wake up core1 // wake up core1