Add Urukul PLL lock timeout failure

Signed-off-by: Egor Savkin <es@m-labs.hk>

src/hw/clocker.md

@@ -19,7 +19,7 @@ Put the `ext_ref_frequency` field into the JSON description if the Kasli is goin
 
 On peripherals you should choose `"clk_sel": 2` on connected devices.
 
-## Setup
+## Setup external clocker
 
 For tests, you may need an external RF generator, depending on customer needs.
 Here is example setup for SynthNV RF signal generator:

src/hw/urukul.md

@@ -103,3 +103,13 @@ ValueError: Urukul proto_rev mismatch
 ```
 
 Check the ports are connected respectively to the JSON description.
+
+### PLL lock timeout
+
+```pycon
+ValueError: PLL lock timeout
+```
+
+This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the customer needs,
+and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly and `EXT`/`INT` pin 
+matches real clocker source.