From 716b36831998153f184ed7cee80e487eb8f849aa Mon Sep 17 00:00:00 2001 From: Egor Savkin Date: Mon, 27 Mar 2023 12:23:13 +0800 Subject: [PATCH] Add Urukul PLL lock timeout failure Signed-off-by: Egor Savkin --- src/hw/clocker.md | 2 +- src/hw/urukul.md | 12 +++++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/hw/clocker.md b/src/hw/clocker.md index c94d629..3712f11 100644 --- a/src/hw/clocker.md +++ b/src/hw/clocker.md @@ -19,7 +19,7 @@ Put the `ext_ref_frequency` field into the JSON description if the Kasli is goin On peripherals you should choose `"clk_sel": 2` on connected devices. -## Setup +## Setup external clocker For tests, you may need an external RF generator, depending on customer needs. Here is example setup for SynthNV RF signal generator: diff --git a/src/hw/urukul.md b/src/hw/urukul.md index f71c3b8..516d62f 100644 --- a/src/hw/urukul.md +++ b/src/hw/urukul.md @@ -102,4 +102,14 @@ and if it is connected to the [Clocker](clocker.md), check that clocker receives ValueError: Urukul proto_rev mismatch ``` -Check the ports are connected respectively to the JSON description. \ No newline at end of file +Check the ports are connected respectively to the JSON description. + +### PLL lock timeout + +```pycon +ValueError: PLL lock timeout +``` + +This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the customer needs, +and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly and `EXT`/`INT` pin +matches real clocker source. \ No newline at end of file