Yann Sionneau e9092edb98 Remove one RTIO out channel to free up some space for travis builds to succeed		2015-03-30 19:51:52 +08:00
..
artiq_kc705.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
artiq_pipistrello.py	add ARTIQMidiSoC based on pipistrello	2015-03-19 11:37:15 -06:00
artiq_ppro.py	Remove one RTIO out channel to free up some space for travis builds to succeed	2015-03-30 19:51:52 +08:00