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artiq/doc/manual
Sebastien Bourdeauducq 99d530e498 targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA 2014-12-01 17:31:35 +08:00
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Makefile doc: add sphinx infrastructure 2014-09-18 17:45:54 +08:00
conf.py doc: add sphinx infrastructure 2014-09-18 17:45:54 +08:00
core_drivers_reference.rst doc: some precisions about controllers 2014-10-28 11:43:06 +08:00
core_language_reference.rst doc/manual: split core/controller drivers 2014-10-27 16:41:48 +08:00
drivers_reference.rst manual/drivers_reference: add lda 2014-11-29 11:04:13 +08:00
fpga_board_ports.rst targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA 2014-12-01 17:31:35 +08:00
getting_started.rst more TTL channels and larger input FIFOs on Papilio Pro 2014-11-30 15:50:57 +08:00
index.rst doc/manual: add ports to index 2014-11-21 18:08:40 -08:00
installing.rst doc/manual/installing: add missing cd 2014-11-27 22:27:18 +08:00
management_reference.rst pc_rpc: document 2014-10-27 13:50:32 +08:00
writing_a_driver.rst frontend: rename files to avoid conflicts 2014-12-01 15:20:35 +08:00