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artiq
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soc
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Sébastien Bourdeauducq
3636025e69
pipistrello: smaller L2 cache
2015-06-18 09:49:52 -06:00
..
artiq_kc705.py
gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache
2015-06-18 12:18:03 +02:00
artiq_pipistrello.py
pipistrello: smaller L2 cache
2015-06-18 09:49:52 -06:00