artiq

History

Sebastien Bourdeauducq 82cdb7f933 typo		2020-01-21 10:07:13 +08:00
..
kasli	urukul: rework EEPROM synchronization. Closes #1372	2019-11-05 18:56:10 +08:00
kasli_drtioswitching	examples: use default IP addresses for boards	2019-10-16 16:18:30 +08:00
kasli_sawgmaster	typo	2020-01-21 10:07:13 +08:00
kasli_suservo	suservo: extract boilerplate	2018-06-01 15:37:07 +00:00
kc705_nist_clock	examples/kc705: fix dds_test	2019-10-17 07:37:00 +08:00
no_hardware	use sipyco (#585 )	2019-11-10 15:55:17 +08:00
sayma_master	examples/sayma_master: update device_db	2019-10-16 18:49:25 +08:00
artiq_ipython_notebook.ipynb	fix device_db alias corner case bugs. Closes #1140	2019-11-14 16:22:45 +08:00
fit_image.py	ship examples with package	2016-04-05 13:59:39 +08:00
README.rst	examples: Add README	2019-12-17 13:35:19 +00:00
remote_exec_controller.py	use sipyco (#585 )	2019-11-10 15:55:17 +08:00

README.rst

ARTIQ experiment examples
=========================

This directory contains several sample ARTIQ master configurations
and associated experiments that illustrate basic usage of various
hardware and software features.

New users might want to peruse the ``no_hardware`` directory to
explore the argument/dataset machinery without needing access to
hardware, and the ``kc705_nist_clock`` directory for inspiration
on how to coordinate between host and FPGA core device code.