artiq/soc/targets
2015-04-02 16:53:57 +08:00
..
artiq_kc705.py targets/kc705: dual-CPU design 2015-04-02 16:53:57 +08:00
artiq_pipistrello.py add ARTIQMidiSoC based on pipistrello 2015-03-19 11:37:15 -06:00
artiq_ppro.py Remove one RTIO out channel to free up some space for travis builds to succeed 2015-03-30 19:51:52 +08:00