Commit Graph

1102 Commits

Author SHA1 Message Date
eeb2790243 examples: use new features 2014-12-19 15:20:19 +08:00
5d40c2431e py2llvm: support type merge with empty list 2014-12-19 15:19:59 +08:00
a9b28dff36 transforms/lower_units: support empty list 2014-12-19 14:40:20 +08:00
5522378c1c support units in lists 2014-12-19 14:34:23 +08:00
0d10ae7580 rpc: support all data types as parameters 2014-12-19 12:46:24 +08:00
44e7b99792 py2llvm/VNone: bugfixes 2014-12-19 12:43:13 +08:00
f31386d15d py2llvm: len() support on lists 2014-12-18 11:13:50 +08:00
8af0301185 transforms/tools/value_to_ast: list support 2014-12-17 22:22:44 +08:00
f3b727b59d py2llvm: replace array with list 2014-12-17 21:54:10 +08:00
6ca39f7415 management/scheduler: improve periodic timing precision 2014-12-11 15:57:41 +08:00
d315268ddb move controllers/clients to frontend 2014-12-11 14:10:15 +08:00
c3953d85d5 master/client: periodic schedule support 2014-12-10 19:11:13 +08:00
347410afa2 master/client: queue display and cancellations 2014-12-10 13:04:18 +08:00
0dc4eb02ae setup: install frontend tools, remove nosetest dependency, minor fixes 2014-12-10 12:13:10 +08:00
87fdad97ca devices/lda: break off main function 2014-12-10 12:01:31 +08:00
eb42cf2bb4 doc/manual/installing: LLVM_CONFIG_PATH does not work with the llvmlite ffi makefile. Use PATH instead. 2014-12-10 10:52:38 +08:00
46e78a4ff1 doc/manual/installing: fix paths (thanks Joe) 2014-12-10 10:46:03 +08:00
08f2aa8503 management/scheduler: replace queue with transparent list + semaphore 2014-12-09 16:26:50 +08:00
059608d1fd dds: fix phase modes 2014-12-09 13:50:33 +08:00
9628e1d013 manual/installing: remove useless cd 2014-12-09 11:28:38 +08:00
cb48dba29c coredevice: fix external clock ref_period computation 2014-12-09 11:22:55 +08:00
597fe57fb3 pyon: unit support 2014-12-09 10:48:47 +08:00
e814da1ba3 master/client: use dpdb and file import 2014-12-08 19:22:02 +08:00
123656e2cd fractions: fix comparison 2014-12-08 19:21:16 +08:00
72c24ba320 identify_controller -> artiq_ctlid 2014-12-08 16:12:39 +08:00
fd28bfbb7c artiq_run: reference module by filename 2014-12-08 16:11:31 +08:00
bfe980d458 py2llvm: distinguish between llvmlite Module and ModuleRef 2014-12-06 15:14:39 +08:00
b830dd527c test/py2llvm: pep8 2014-12-06 14:54:41 +08:00
9165031fd5 test/py2llvm: support 32-bit machines 2014-12-06 14:52:33 +08:00
0e9c9b25b0 README: update 2014-12-05 17:14:52 +08:00
159f632a65 switch to llvmlite 2014-12-05 17:05:43 +08:00
b93b969e2a doc/pc_rpc: add warning about mutable types 2014-12-04 18:04:54 +08:00
044756287f test: add serialization 2014-12-04 17:52:22 +08:00
4c7749bd01 pyon: partial JSON compatibility 2014-12-03 23:46:59 +08:00
fd8f3be946 pyon: pretty printing 2014-12-03 23:25:51 +08:00
2a95d27770 device and parameter database 2014-12-03 18:20:30 +08:00
a41009f92a coredevice/comm_dummy: support clock-switching functions 2014-12-03 18:16:18 +08:00
5b8f34bae2 language/core/kernel: support return values 2014-12-03 17:21:26 +08:00
85b4d70ced pyon: add file I/O functions 2014-12-03 17:18:43 +08:00
6de650a701 doc/manual: minor fixes 2014-12-02 19:23:15 +08:00
2a843ea436 language: replace AutoContext 'parameter' string with abstract attributes
This allows specifying default values for parameters, and other data.
2014-12-02 17:19:05 +08:00
83d3b97b23 coredevice/comm_serial: give up on garbage received after baudrate change 2014-12-02 16:04:41 +08:00
cad5933709 transforms/inline: do not writeback bool 2014-12-02 15:53:41 +08:00
649fedd656 coredevice/core: fix recover_underflow 2014-12-02 15:31:09 +08:00
fc690ead75 runtime: support clock switching 2014-12-02 14:06:32 +08:00
94218f785e comm_serial: cleanup 2014-12-02 11:09:02 +08:00
Yann Sionneau
20adb57140 comm_serial: allow to use dynamic baudrate 2014-12-02 10:42:14 +08:00
Yann Sionneau
3ff3afe696 manual: use theme options which looks like m-labs web site 2014-12-02 10:32:27 +08:00
Yann Sionneau
0c20445413 lda: allow to simulate without needing hidapi
This also fixes some old style string formating
2014-12-01 19:39:13 +08:00
c591f1a74d targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG 2014-12-01 18:53:29 +08:00