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doc/manual: minor fixes

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Sebastien Bourdeauducq 2014-12-02 19:23:15 +08:00
parent 2a843ea436
commit 6de650a701
2 changed files with 6 additions and 4 deletions

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@ -1,6 +1,8 @@
Core language reference
=======================
The most commonly used features from those modules can be imported with ``from artiq import *``.
:mod:`artiq.language.core` module
---------------------------------
@ -8,7 +10,7 @@ Core language reference
:members:
:mod:`artiq.language.context` module
---------------------------------
------------------------------------
.. automodule:: artiq.language.context
:members:

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@ -8,11 +8,11 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
* Install the FPGA vendor tools (e.g. Xilinx ISE and/or Vivado):
Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Papilio Pro) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
* Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Papilio Pro) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
The Papilio Pro is supported by Webpack, the KC705 is not.
* The Papilio Pro is supported by Webpack, the KC705 is not.
During the Xilinx toolchain installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
* During the Xilinx toolchain installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
* Create a development directory: ::