8 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	2881d5f00a	gateware: add RTIO clock generator	2015-07-02 18:20:26 +02:00
Robert Jördens	d1c4cf0b78	pipistrello: update rtio channel doc	2015-06-29 12:21:54 -06:00
Sebastien Bourdeauducq	938e1c2842	Remove UP support. ... The only advantage of UP is to support the Papilio Pro, but that port is also very limited in other ways and the Pipistrello provides a more reasonable platform that also supports AMP. On the other hand, RPCs on UP are difficult to implement with the session.c protocol system (without an operating system or coroutines), along with many other minor difficulties and maintainance issues. Planned features such as watchdogs in the core device are also difficult on UP.	2015-04-27 20:43:45 +08:00
Sebastien Bourdeauducq	c8039e9dd2	doc: update Papilio Pro info	2015-04-07 00:09:08 +08:00
Sebastien Bourdeauducq	c591f1a74d	targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG	2014-12-01 18:53:29 +08:00
Sebastien Bourdeauducq	99d530e498	targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA	2014-12-01 17:31:35 +08:00
Sebastien Bourdeauducq	1f6441948d	more TTL channels and larger input FIFOs on Papilio Pro	2014-11-30 15:50:57 +08:00
Sebastien Bourdeauducq	8d59f843fb	doc/manual: add FPGA board info and TTL line assignments	2014-11-21 16:39:22 -08:00