forked from M-Labs/artiq
ddb_template: support different satellite targets
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0c1b572872
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@ -11,17 +11,20 @@ from artiq.coredevice import jsondesc
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from artiq.coredevice.phaser import PHASER_GW_MIQRO, PHASER_GW_BASE
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def process_header(output, description):
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def get_cpu_target(description):
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if description.get("type", None) == "shuttler":
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return "rv32g"
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if description["target"] == "kasli":
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if description["hw_rev"] in ("v1.0", "v1.1"):
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cpu_target = "rv32ima"
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return "rv32ima"
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else:
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cpu_target = "rv32g"
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return "rv32g"
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elif description["target"] == "kasli_soc":
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cpu_target = "cortexa9"
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return "cortexa9"
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else:
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raise NotImplementedError
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def process_header(output, description):
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print(textwrap.dedent("""
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# Autogenerated for the {variant} variant
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core_addr = "{core_addr}"
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@ -57,6 +60,8 @@ def process_header(output, description):
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"class": "CoreDMA"
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}},
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"satellite_cpu_targets": {{}},
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"i2c_switch0": {{
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"type": "local",
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"module": "artiq.coredevice.i2c",
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@ -74,7 +79,7 @@ def process_header(output, description):
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variant=description["variant"],
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core_addr=description["core_addr"],
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ref_period=1/(8*description["rtio_frequency"]),
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cpu_target=cpu_target),
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cpu_target=get_cpu_target(description)),
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file=output)
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@ -753,6 +758,7 @@ def process(output, primary_description, satellites):
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drtio_peripherals.extend(satellite_drtio_peripherals)
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print("# DEST#{} peripherals".format(destination), file=output)
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print("device_db[\"satellite_cpu_targets\"][{}] = \"{}\"".format(destination, get_cpu_target(description)), file=output)
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rtio_offset = destination << 16
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for peripheral in peripherals:
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n_channels = pm.process(rtio_offset, peripheral)
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@ -760,6 +766,7 @@ def process(output, primary_description, satellites):
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for peripheral in drtio_peripherals:
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print("# DEST#{} peripherals".format(peripheral["drtio_destination"]), file=output)
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print("device_db[\"satellite_cpu_targets\"][{}] = \"{}\"".format(peripheral["drtio_destination"], get_cpu_target(peripheral)), file=output)
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processor = getattr(pm, "process_"+str(peripheral["type"]))
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processor(peripheral)
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