ttl_serdes_7series: cleanup indentation

Inconsistent with other code and confuses text editors.

artiq/gateware/rtio/phy/ttl_serdes_7series.py

@@ -37,6 +37,7 @@ class _OSERDESE2_8X(Module):
                 i_T=self.t_out,
                 io_IO=pad, io_IOB=pad_n)
 
+
 class _ISERDESE2_8X(Module):
     def __init__(self, pad, pad_n=None):
         self.o = Signal(8)