From fa3b40141d5d53b478323a4c6906d3932c6fae8d Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 31 Jan 2019 15:10:11 +0800
Subject: [PATCH] hmc830_7043: document sayma clock muxes

---
 artiq/firmware/libboard_artiq/hmc830_7043.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs
index 2348f6091..2a1654134 100644
--- a/artiq/firmware/libboard_artiq/hmc830_7043.rs
+++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs
@@ -9,10 +9,10 @@ mod clock_mux {
     pub fn init() {
         unsafe {
             csr::clock_mux::out_write(
-                1*CLK_SRC_EXT_SEL |  // use ext clk from sma
-                1*REF_CLK_SRC_SEL |
-                1*DAC_CLK_SRC_SEL |
-                0*REF_LO_CLK_SEL);
+                1*CLK_SRC_EXT_SEL |  // 1= ext clk from sma, 0= RF backplane (IC46) to IC45
+                1*REF_CLK_SRC_SEL |  // 1= low-noise clock, 0= Si5324 output (IC45) to HMC830
+                1*DAC_CLK_SRC_SEL |  // 1= HMC830 output, 1= clock mezzanine (IC54) to HMC7043 and J58/J59
+                0*REF_LO_CLK_SEL);   // 1= clock mezzanine, 0= HMC830 input  (IC52) to AFEs and J56/J57
         }
     }
 }