forked from M-Labs/artiq
satman: use new SYSREF code
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parent
32c95ac034
commit
f8c17528e7
@ -249,10 +249,6 @@ fn drtio_link_rx_up() -> bool {
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}
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const SIPHASER_PHASE: u16 = 32;
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#[cfg(has_ad9154)]
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const SYSREF_PHASE_FPGA: u16 = 54;
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#[cfg(has_ad9154)]
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const SYSREF_PHASE_DAC: u16 = 61;
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#[no_mangle]
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pub extern fn main() -> i32 {
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@ -292,7 +288,14 @@ pub extern fn main() -> i32 {
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#[cfg(has_ad9154)]
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{
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if !ad9154_initialized {
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board_artiq::ad9154::init(SYSREF_PHASE_FPGA, SYSREF_PHASE_DAC);
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board_artiq::ad9154::jesd_unreset();
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board_artiq::ad9154::init();
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align(1) {
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error!("failed to align SYSREF at FPGA: {}", e);
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}
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
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error!("failed to align SYSREF at DAC: {}", e);
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}
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ad9154_initialized = true;
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}
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}
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@ -306,9 +309,10 @@ pub extern fn main() -> i32 {
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{
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if drtio_tsc_loaded() {
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// Expected alignment: 1 RTIO clock period
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hmc830_7043::hmc7043::sysref_rtio_align(
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SYSREF_PHASE_FPGA,
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hmc830_7043::hmc7043::FPGA_CLK_DIV);
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align(
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hmc830_7043::hmc7043::FPGA_CLK_DIV) {
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error!("failed to align SYSREF at FPGA: {}", e);
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}
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}
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}
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}
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