forked from M-Labs/artiq
sayma: automated DAC SYSREF phase calibration
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dbcf2fe9b4
commit
32c95ac034
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@ -1,6 +1,5 @@
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use board_misoc::{csr, clock};
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use ad9154_reg;
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use hmc830_7043::hmc7043;
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fn spi_setup(dacno: u8) {
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unsafe {
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@ -688,7 +687,7 @@ fn dac_cfg_retry(dacno: u8) -> Result<(), &'static str> {
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}
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}
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fn dac_get_sync_error(dacno: u8) -> u16 {
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pub fn dac_get_sync_error(dacno: u8) -> u16 {
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spi_setup(dacno);
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let sync_error = ((read(ad9154_reg::SYNC_CURRERR_L) as u16) |
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((read(ad9154_reg::SYNC_CURRERR_H) as u16) << 8))
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@ -696,73 +695,24 @@ fn dac_get_sync_error(dacno: u8) -> u16 {
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sync_error
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}
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fn dac_sysref_scan(dacno: u8, center_phase: u16) {
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let mut margin_minus = None;
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let mut margin_plus = None;
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info!("AD9154-{} SYSREF scan...", dacno);
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hmc7043::sysref_offset_dac(dacno, center_phase);
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clock::spin_us(10000);
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let mut sync_error_last = dac_get_sync_error(dacno);
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for d in 0..128 {
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hmc7043::sysref_offset_dac(dacno, center_phase - d);
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clock::spin_us(10000);
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let sync_error = dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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info!(" sync error-: {} -> {}", sync_error_last, sync_error);
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margin_minus = Some(d);
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break;
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}
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}
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hmc7043::sysref_offset_dac(dacno, center_phase);
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clock::spin_us(10000);
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sync_error_last = dac_get_sync_error(dacno);
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for d in 0..128 {
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hmc7043::sysref_offset_dac(dacno, center_phase + d);
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clock::spin_us(10000);
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let sync_error = dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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info!(" sync error+: {} -> {}", sync_error_last, sync_error);
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margin_plus = Some(d);
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break;
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}
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}
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if margin_minus.is_some() && margin_plus.is_some() {
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let margin_minus = margin_minus.unwrap();
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let margin_plus = margin_plus.unwrap();
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info!(" margins: -{} +{}", margin_minus, margin_plus);
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if margin_minus < 10 || margin_plus < 10 {
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error!("SYSREF margins are too small");
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}
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} else {
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error!("Unable to determine SYSREF margins");
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}
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}
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fn init_dac(dacno: u8, sysref_phase: u16) -> Result<(), &'static str> {
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fn init_dac(dacno: u8) -> Result<(), &'static str> {
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let dacno = dacno as u8;
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// Reset the DAC, detect and configure it
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dac_reset(dacno);
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dac_detect(dacno)?;
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dac_cfg_retry(dacno)?;
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// Run the PRBS, STPL and SYSREF scan tests
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dac_prbs(dacno)?;
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dac_stpl(dacno, 4, 2)?;
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dac_sysref_scan(dacno, sysref_phase);
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// Set SYSREF phase and reconfigure the DAC
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hmc7043::sysref_offset_dac(dacno, sysref_phase);
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dac_cfg_retry(dacno)?;
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Ok(())
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}
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pub fn init(sysref_phase_dac: u16) {
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pub fn init() {
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for dacno in 0..csr::AD9154.len() {
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// We assume DCLK and SYSREF traces are matched on the PCB
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// (they are on Sayma) so only one phase is needed.
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match init_dac(dacno as u8, sysref_phase_dac) {
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match init_dac(dacno as u8) {
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Ok(_) => (),
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Err(e) => error!("failed to initialize AD9154-{}: {}", dacno, e)
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}
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@ -1,8 +1,7 @@
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use board_misoc::csr;
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use board_misoc::config;
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use board_misoc::{csr, clock, config};
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use hmc830_7043::hmc7043;
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use ad9154;
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fn sysref_sample() -> bool {
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unsafe { csr::sysref_sampler::sample_result_read() == 1 }
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@ -142,3 +141,127 @@ pub fn sysref_auto_rtio_align(expected_align: u16) -> Result<(), &'static str> {
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};
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sysref_rtio_align(phase_offset, expected_align)
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}
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fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {
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info!("calibrating SYSREF phase at DAC-{}...", dacno);
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let mut d = 0;
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let dmin;
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let dmax;
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hmc7043::sysref_offset_dac(dacno, d);
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clock::spin_us(10000);
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let sync_error_last = ad9154::dac_get_sync_error(dacno);
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loop {
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hmc7043::sysref_offset_dac(dacno, d);
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clock::spin_us(10000);
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let sync_error = ad9154::dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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dmin = d;
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break;
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}
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d += 1;
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if d > 128 {
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return Err("no sync errors found when scanning delay");
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}
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}
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d += 5; // get away from jitter
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hmc7043::sysref_offset_dac(dacno, d);
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clock::spin_us(10000);
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let sync_error_last = ad9154::dac_get_sync_error(dacno);
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loop {
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hmc7043::sysref_offset_dac(dacno, d);
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clock::spin_us(10000);
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let sync_error = ad9154::dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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dmax = d;
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break;
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}
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d += 1;
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if d > 128 {
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return Err("no sync errors found when scanning delay");
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}
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}
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let phase = (dmin+dmax)/2;
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info!(" ...done, min={}, max={}, result={}", dmin, dmax, phase);
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Ok(phase)
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}
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fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> {
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let mut margin_minus = None;
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let mut margin_plus = None;
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info!("verifying SYSREF margins at DAC-{}...", dacno);
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hmc7043::sysref_offset_dac(dacno, phase);
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clock::spin_us(10000);
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let sync_error_last = ad9154::dac_get_sync_error(dacno);
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for d in 0..128 {
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hmc7043::sysref_offset_dac(dacno, phase - d);
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clock::spin_us(10000);
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let sync_error = ad9154::dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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info!(" sync error-: {} -> {}", sync_error_last, sync_error);
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margin_minus = Some(d);
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break;
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}
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}
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hmc7043::sysref_offset_dac(dacno, phase);
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clock::spin_us(10000);
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let sync_error_last = ad9154::dac_get_sync_error(dacno);
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for d in 0..128 {
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hmc7043::sysref_offset_dac(dacno, phase + d);
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clock::spin_us(10000);
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let sync_error = ad9154::dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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info!(" sync error+: {} -> {}", sync_error_last, sync_error);
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margin_plus = Some(d);
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break;
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}
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}
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if margin_minus.is_some() && margin_plus.is_some() {
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let margin_minus = margin_minus.unwrap();
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let margin_plus = margin_plus.unwrap();
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info!(" margins: -{} +{}", margin_minus, margin_plus);
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if margin_minus < 10 || margin_plus < 10 {
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return Err("SYSREF margins at DAC are too small, board needs recalibration");
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}
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} else {
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return Err("Unable to determine SYSREF margins at DAC");
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}
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// Leave SYSREF at the correct setting
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hmc7043::sysref_offset_dac(dacno, phase);
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Ok(())
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}
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pub fn sysref_auto_dac_align() -> Result<(), &'static str> {
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// We assume that DAC SYSREF traces are length-matched so only one phase
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// value is needed, and we use DAC-0 as calibration reference.
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let entry = config::read_str("sysref_phase_dac", |r| r.map(|s| s.parse()));
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let phase = match entry {
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Ok(Ok(phase)) => phase,
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_ => {
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let phase = sysref_cal_dac(0)?;
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if let Err(e) = config::write_int("sysref_phase_dac", phase as u32) {
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error!("failed to update DAC SYSREF phase in config: {}", e);
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}
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phase
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}
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};
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for dacno in 0..csr::AD9154.len() {
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sysref_dac_align(dacno as u8, phase)?;
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}
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Ok(())
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}
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@ -56,9 +56,6 @@ mod moninj;
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#[cfg(has_rtio_analyzer)]
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mod analyzer;
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#[cfg(has_ad9154)]
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const SYSREF_PHASE_DAC: u16 = 94;
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fn startup() {
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irq::set_mask(0);
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irq::set_ie(true);
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@ -114,10 +111,13 @@ fn startup() {
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#[cfg(has_ad9154)]
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{
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board_artiq::ad9154::jesd_unreset();
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board_artiq::ad9154::init();
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align(1) {
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error!("failed to align SYSREF at FPGA: {}", e);
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}
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board_artiq::ad9154::init(SYSREF_PHASE_DAC);
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
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error!("failed to align SYSREF at DAC: {}", e);
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}
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}
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#[cfg(has_allaki_atts)]
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board_artiq::hmc542::program_all(8/*=4dB*/);
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