srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

serwb/genphy: add device parameter (not used here, but this way all the phys share the same parameters), scrambling is also now always enabled.

This commit is contained in:
Florent Kermarrec 2018-05-15 23:51:14 +02:00
parent 2c627cd061
commit f8a9dd930b
3 changed files with 5 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
artiq/gateware/serwb/genphy.py
View File

@ -317,8 +317,6 @@ class _SerdesControl(Module, AutoCSR):
self.bitslip = CSRStatus(6) self.bitslip = CSRStatus(6)
self.scrambling_enable = CSRStorage()
self.prbs_error = Signal() self.prbs_error = Signal()
self.prbs_start = CSR() self.prbs_start = CSR()
self.prbs_cycles = CSRStorage(32) self.prbs_cycles = CSRStorage(32)
@ -369,7 +367,7 @@ class _SerdesControl(Module, AutoCSR):
class SERWBPHY(Module, AutoCSR): class SERWBPHY(Module, AutoCSR):
def __init__(self, pads, mode="master", init_timeout=2**16): def __init__(self, device, pads, mode="master", init_timeout=2**16):
self.sink = sink = stream.Endpoint([("data", 32)]) self.sink = sink = stream.Endpoint([("data", 32)])
self.source = source = stream.Endpoint([("data", 32)]) self.source = source = stream.Endpoint([("data", 32)])
assert mode in ["master", "slave"] assert mode in ["master", "slave"]
@ -381,13 +379,8 @@ class SERWBPHY(Module, AutoCSR):
self.submodules.control = _SerdesControl(self.serdes, self.init, mode) self.submodules.control = _SerdesControl(self.serdes, self.init, mode)
# scrambling # scrambling
scrambler = Scrambler() self.submodules.scrambler = scrambler = Scrambler()
descrambler = Descrambler() self.submodules.descrambler = descrambler = Descrambler()
self.submodules += scrambler, descrambler
self.comb += [
scrambler.enable.eq(self.control.scrambling_enable.storage),
descrambler.enable.eq(self.control.scrambling_enable.storage)
]
# tx dataflow # tx dataflow
self.comb += \ self.comb += \

2
artiq/gateware/targets/sayma_amc.py
View File

@ -174,7 +174,7 @@ class Standalone(MiniSoC, AMPSoC):
# AMC/RTM serwb # AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb") serwb_pads = platform.request("amc_rtm_serwb")
serwb_phy_amc = serwb.genphy.SERWBPHY(serwb_pads, mode="master") serwb_phy_amc = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="master")
self.submodules.serwb_phy_amc = serwb_phy_amc self.submodules.serwb_phy_amc = serwb_phy_amc
self.csr_devices.append("serwb_phy_amc") self.csr_devices.append("serwb_phy_amc")

2
artiq/gateware/targets/sayma_rtm.py
View File

@ -151,7 +151,7 @@ class SaymaRTM(Module):
# AMC/RTM serwb # AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb") serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk_p, 8.) platform.add_period_constraint(serwb_pads.clk_p, 8.)
serwb_phy_rtm = serwb.genphy.SERWBPHY(serwb_pads, mode="slave") serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += [ self.comb += [
self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk), self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),