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serwb/scrambler: simplify and set scrambler input data to 0 when sink.stb == 0

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This commit is contained in:
Florent Kermarrec 2018-05-15 23:49:17 +02:00
parent 7fe49a78d2
commit 2c627cd061
2 changed files with 23 additions and 48 deletions
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67
artiq/gateware/serwb/scrambler.py
View File

@ -31,75 +31,51 @@ class _Scrambler(Module):
class Scrambler(Module):
def __init__(self, sync_interval=1024):
self.enable = Signal()
def __init__(self, sync_interval=2**10):
self.sink = sink = stream.Endpoint([("data", 32)])
self.source = source = stream.Endpoint([("d", 32), ("k", 4)])
# # #
# scrambler
# Scrambler
self.submodules.scrambler = scrambler = _Scrambler(32)
# insert K.29.7 as sync character
# every sync_interval cycles
# Insert K29.7 SYNC character every "sync_interval" cycles
count = Signal(max=sync_interval)
self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="DISABLE"))
self.comb += fsm.reset.eq(~self.enable)
fsm.act("DISABLE",
sink.connect(source, omit={"data"}),
source.k.eq(0b0000),
source.d.eq(sink.data),
NextState("SYNC")
)
fsm.act("SYNC",
scrambler.reset.eq(1),
self.sync += If(source.ack, count.eq(count + 1))
self.comb += [
source.stb.eq(1),
source.k[0].eq(1),
source.d[:8].eq(K(29, 7)),
NextValue(count, 0),
If(source.ack,
NextState("DATA")
)
)
fsm.act("DATA",
scrambler.i.eq(sink.data),
sink.ack.eq(source.ack),
source.stb.eq(1),
source.d.eq(scrambler.o),
If(source.stb & source.ack,
scrambler.ce.eq(1),
NextValue(count, count + 1),
If(count == (sync_interval - 1),
NextState("SYNC")
If(count == 0,
scrambler.reset.eq(1),
source.k.eq(0b1),
source.d.eq(K(29, 7)),
).Else(
If(sink.stb, scrambler.i.eq(sink.data)),
source.k.eq(0),
source.d.eq(scrambler.o),
If(source.ack,
sink.ack.eq(1),
scrambler.ce.eq(1)
)
)
)
]
class Descrambler(Module):
def __init__(self):
self.enable = Signal()
self.sink = sink = stream.Endpoint([("d", 32), ("k", 4)])
self.source = source = stream.Endpoint([("data", 32)])
# # #
# descrambler
# Descrambler
self.submodules.descrambler = descrambler = _Scrambler(32)
self.comb += descrambler.i.eq(sink.d)
# detect K29.7 and synchronize descrambler
self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="DISABLE"))
self.comb += fsm.reset.eq(~self.enable)
fsm.act("DISABLE",
sink.connect(source, omit={"d", "k"}),
source.data.eq(sink.d),
NextState("SYNC_DATA")
)
fsm.act("SYNC_DATA",
# Detect K29.7 SYNC character and synchronize Descrambler
self.comb += \
If(sink.stb,
If((sink.k == 1) & (sink.d == K(29,7)),
If((sink.k == 0b1) & (sink.d == K(29,7)),
sink.ack.eq(1),
descrambler.reset.eq(1)
).Else(
@ -111,4 +87,3 @@ class Descrambler(Module):
)
)
)
)

4
artiq/gateware/test/serwb/test_serwb_core.py
View File

@ -101,7 +101,7 @@ class DUTCore(Module):
class TestSERWBCore(unittest.TestCase):
def test_scrambler(self):
def generator(dut):
def generator(dut, rand_level=50):
# prepare test
prng = random.Random(42)
i = 0
@ -115,7 +115,7 @@ class TestSERWBCore(unittest.TestCase):
yield dut.scrambler.sink.data.eq(i)
# check
yield dut.descrambler.source.ack.eq(prng.randrange(2))
yield dut.descrambler.source.ack.eq(prng.randrange(prng.randrange(100) > rand_level)
if (yield dut.descrambler.source.stb) & (yield dut.descrambler.source.ack):
current_data = (yield dut.descrambler.source.data)
if (current_data != (last_data + 1)):