forked from M-Labs/artiq
serwb/scrambler: simplify and set scrambler input data to 0 when sink.stb == 0
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@ -31,75 +31,51 @@ class _Scrambler(Module):
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class Scrambler(Module):
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def __init__(self, sync_interval=1024):
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self.enable = Signal()
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def __init__(self, sync_interval=2**10):
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self.sink = sink = stream.Endpoint([("data", 32)])
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self.source = source = stream.Endpoint([("d", 32), ("k", 4)])
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# # #
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# scrambler
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# Scrambler
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self.submodules.scrambler = scrambler = _Scrambler(32)
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# insert K.29.7 as sync character
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# every sync_interval cycles
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# Insert K29.7 SYNC character every "sync_interval" cycles
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count = Signal(max=sync_interval)
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="DISABLE"))
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self.comb += fsm.reset.eq(~self.enable)
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fsm.act("DISABLE",
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sink.connect(source, omit={"data"}),
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source.k.eq(0b0000),
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source.d.eq(sink.data),
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NextState("SYNC")
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)
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fsm.act("SYNC",
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scrambler.reset.eq(1),
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self.sync += If(source.ack, count.eq(count + 1))
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self.comb += [
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source.stb.eq(1),
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source.k[0].eq(1),
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source.d[:8].eq(K(29, 7)),
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NextValue(count, 0),
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If(source.ack,
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NextState("DATA")
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)
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)
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fsm.act("DATA",
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scrambler.i.eq(sink.data),
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sink.ack.eq(source.ack),
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source.stb.eq(1),
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source.d.eq(scrambler.o),
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If(source.stb & source.ack,
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scrambler.ce.eq(1),
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NextValue(count, count + 1),
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If(count == (sync_interval - 1),
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NextState("SYNC")
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If(count == 0,
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scrambler.reset.eq(1),
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source.k.eq(0b1),
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source.d.eq(K(29, 7)),
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).Else(
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If(sink.stb, scrambler.i.eq(sink.data)),
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source.k.eq(0),
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source.d.eq(scrambler.o),
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If(source.ack,
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sink.ack.eq(1),
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scrambler.ce.eq(1)
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)
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)
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)
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]
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class Descrambler(Module):
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def __init__(self):
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self.enable = Signal()
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self.sink = sink = stream.Endpoint([("d", 32), ("k", 4)])
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self.source = source = stream.Endpoint([("data", 32)])
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# # #
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# descrambler
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# Descrambler
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self.submodules.descrambler = descrambler = _Scrambler(32)
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self.comb += descrambler.i.eq(sink.d)
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# detect K29.7 and synchronize descrambler
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="DISABLE"))
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self.comb += fsm.reset.eq(~self.enable)
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fsm.act("DISABLE",
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sink.connect(source, omit={"d", "k"}),
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source.data.eq(sink.d),
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NextState("SYNC_DATA")
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)
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fsm.act("SYNC_DATA",
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# Detect K29.7 SYNC character and synchronize Descrambler
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self.comb += \
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If(sink.stb,
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If((sink.k == 1) & (sink.d == K(29,7)),
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If((sink.k == 0b1) & (sink.d == K(29,7)),
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sink.ack.eq(1),
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descrambler.reset.eq(1)
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).Else(
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@ -111,4 +87,3 @@ class Descrambler(Module):
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)
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)
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)
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)
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@ -101,7 +101,7 @@ class DUTCore(Module):
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class TestSERWBCore(unittest.TestCase):
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def test_scrambler(self):
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def generator(dut):
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def generator(dut, rand_level=50):
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# prepare test
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prng = random.Random(42)
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i = 0
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@ -115,7 +115,7 @@ class TestSERWBCore(unittest.TestCase):
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yield dut.scrambler.sink.data.eq(i)
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# check
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yield dut.descrambler.source.ack.eq(prng.randrange(2))
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yield dut.descrambler.source.ack.eq(prng.randrange(prng.randrange(100) > rand_level)
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if (yield dut.descrambler.source.stb) & (yield dut.descrambler.source.ack):
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current_data = (yield dut.descrambler.source.data)
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if (current_data != (last_data + 1)):
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