forked from M-Labs/artiq
rtio.spi: drop unused argument
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@ -5,7 +5,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
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class SPIMaster(Module):
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def __init__(self, pads, onehot=False, **kwargs):
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def __init__(self, pads, **kwargs):
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self.submodules._ll = ClockDomainsRenamer("rio")(
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SPIMasterWB(pads, **kwargs))
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self.submodules._rt2wb = RT2WB(2, self._ll.bus)
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