diff --git a/artiq/gateware/rtio/phy/spi.py b/artiq/gateware/rtio/phy/spi.py
index e72f602c2..92ab7a548 100644
--- a/artiq/gateware/rtio/phy/spi.py
+++ b/artiq/gateware/rtio/phy/spi.py
@@ -5,7 +5,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
 
 
 class SPIMaster(Module):
-    def __init__(self, pads, onehot=False, **kwargs):
+    def __init__(self, pads, **kwargs):
         self.submodules._ll = ClockDomainsRenamer("rio")(
             SPIMasterWB(pads, **kwargs))
         self.submodules._rt2wb = RT2WB(2, self._ll.bus)