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sawg/hbf: tweak pipeline for timing

This commit is contained in:
Robert Jördens 2016-12-08 17:00:53 +01:00
parent b7a308d33d
commit f6071a5812
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/dsp/sawg.py
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@ -177,6 +177,8 @@ class Channel(Module, SatAddMixin):
b.ce.eq(cfg.ce), b.ce.eq(cfg.ce),
u.o.ack.eq(cfg.ce), u.o.ack.eq(cfg.ce),
Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr), Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
b.i.x.eq(hbf[0].o[0]), # FIXME: rip up
b.i.y.eq(hbf[1].o[0]),
] ]
self.sync += [ self.sync += [
hbf[0].i.eq(self.sat_add(a1.xo[0], a2.xo[0], hbf[0].i.eq(self.sat_add(a1.xo[0], a2.xo[0],
@ -185,8 +187,6 @@ class Channel(Module, SatAddMixin):
hbf[1].i.eq(self.sat_add(a1.yo[0], a2.yo[0], hbf[1].i.eq(self.sat_add(a1.yo[0], a2.yo[0],
limits=cfg.limits[1], limits=cfg.limits[1],
clipped=cfg.clipped[1])), clipped=cfg.clipped[1])),
b.i.x.eq(hbf[0].o[0]), # FIXME: rip up
b.i.y.eq(hbf[1].o[0]),
eqh(du.i, u.o.a0), eqh(du.i, u.o.a0),
] ]
# wire up outputs and q_{i,o} exchange # wire up outputs and q_{i,o} exchange