forked from M-Labs/artiq
fir: register multiplier output
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@ -47,7 +47,7 @@ class FIR(Module):
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self.i = Signal((width, True))
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self.o = Signal((width, True))
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n = len(coefficients)
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self.latency = (n + 1)//2 + 1
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self.latency = (n + 1)//2 + 2
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###
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@ -55,18 +55,22 @@ class FIR(Module):
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x = [Signal((width, True)) for _ in range(n)]
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self.sync += [xi.eq(xj) for xi, xj in zip(x, [self.i] + x)]
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# Wire up output
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if shift is None:
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shift = width - 1
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# Make products
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o = []
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for i, c in enumerate(coefficients):
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# simplify for halfband and symmetric filters
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if c == 0 or c in coefficients[i + 1:]:
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continue
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o.append(c*reduce(add, [
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m = Signal((width + shift, True))
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self.sync += m.eq(c*reduce(add, [
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xj for xj, cj in zip(x[::-1], coefficients) if cj == c
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]))
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o.append(m)
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if shift is None:
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shift = width - 1
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# Make sum
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self.sync += self.o.eq(reduce(add, o) >> shift)
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@ -85,7 +89,7 @@ class ParallelFIR(Module):
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# input and output: old to young, decreasing delay
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self.i = [Signal((width, True)) for i in range(p)]
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self.o = [Signal((width, True)) for i in range(p)]
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self.latency = (n + 1)//2//parallelism + 2 # minus .5
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self.latency = (n + 1)//2//parallelism + 3 # minus one sample
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###
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@ -96,16 +100,19 @@ class ParallelFIR(Module):
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if shift is None:
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shift = width - 1
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# wire up each output
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for j in range(p):
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# Make products
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o = []
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for i, c in enumerate(coefficients):
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# simplify for halfband and symmetric filters
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if c == 0 or c in coefficients[i + 1:]:
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continue
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o.append(c*reduce(add, [
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m = Signal((width + shift, True))
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self.sync += m.eq(c*reduce(add, [
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xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c
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]))
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o.append(m)
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# Make sum
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self.sync += self.o[j].eq(reduce(add, o) >> shift)
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