forked from M-Labs/artiq
Remove irgen tests.
These are too hard to write and will be replaced by integration tests of ARTIQ IR generator + LLVM IR generator once the latter gets implemented.
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adf18bb042
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@ -1,7 +0,0 @@
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# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
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# RUN: OutputCheck %s --file-to-check=%t
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# CHECK-L: NoneType input.__modinit__() {
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# CHECK-L: 1:
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# CHECK-L: return NoneType None
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# CHECK-L: }
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@ -1,9 +0,0 @@
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# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
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# RUN: OutputCheck %s --file-to-check=%t
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2 + 2
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# CHECK-L: NoneType input.__modinit__() {
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# CHECK-L: 1:
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# CHECK-L: %2 = int(width=32) eval `2 + 2`
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# CHECK-L: return NoneType None
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# CHECK-L: }
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@ -1,21 +0,0 @@
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# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
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# RUN: OutputCheck %s --file-to-check=%t
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if 1:
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2
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else:
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3
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# CHECK-L: NoneType input.__modinit__() {
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# CHECK-L: 1:
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# CHECK-L: %2 = int(width=32) eval `1`
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# CHECK-L: branch_if int(width=32) %2, ssa.basic_block %3, ssa.basic_block %5
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# CHECK-L: 3:
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# CHECK-L: %4 = int(width=32) eval `2`
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# CHECK-L: branch ssa.basic_block %7
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# CHECK-L: 5:
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# CHECK-L: %6 = int(width=32) eval `3`
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# CHECK-L: branch ssa.basic_block %7
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# CHECK-L: 7:
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# CHECK-L: return NoneType None
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# CHECK-L: }
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@ -1,25 +0,0 @@
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# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
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# RUN: OutputCheck %s --file-to-check=%t
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while 1:
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2
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else:
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3
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4
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# CHECK-L: NoneType input.__modinit__() {
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# CHECK-L: 1:
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# CHECK-L: branch ssa.basic_block %2
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# CHECK-L: 2:
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# CHECK-L: %9 = int(width=32) eval `1`
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# CHECK-L: branch_if int(width=32) %9, ssa.basic_block %5, ssa.basic_block %7
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# CHECK-L: 4:
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# CHECK-L: branch ssa.basic_block %7
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# CHECK-L: 5:
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# CHECK-L: %6 = int(width=32) eval `2`
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# CHECK-L: branch ssa.basic_block %7
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# CHECK-L: 7:
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# CHECK-L: %8 = int(width=32) eval `3`
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# CHECK-L: %13 = int(width=32) eval `4`
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# CHECK-L: return NoneType None
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# CHECK-L: }
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