From f5d9e11b38467a66608c2e16526416fc831d7e8e Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 19 Jul 2015 11:30:53 +0300
Subject: [PATCH] Remove irgen tests.

These are too hard to write and will be replaced by integration
tests of ARTIQ IR generator + LLVM IR generator once the latter
gets implemented.
---
 lit-test/compiler/irgen/empty.py |  7 -------
 lit-test/compiler/irgen/eval.py  |  9 ---------
 lit-test/compiler/irgen/if.py    | 21 ---------------------
 lit-test/compiler/irgen/while.py | 25 -------------------------
 4 files changed, 62 deletions(-)
 delete mode 100644 lit-test/compiler/irgen/empty.py
 delete mode 100644 lit-test/compiler/irgen/eval.py
 delete mode 100644 lit-test/compiler/irgen/if.py
 delete mode 100644 lit-test/compiler/irgen/while.py

diff --git a/lit-test/compiler/irgen/empty.py b/lit-test/compiler/irgen/empty.py
deleted file mode 100644
index 85beee74d..000000000
--- a/lit-test/compiler/irgen/empty.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
-# RUN: OutputCheck %s --file-to-check=%t
-
-# CHECK-L: NoneType input.__modinit__() {
-# CHECK-L: 1:
-# CHECK-L:   return NoneType None
-# CHECK-L: }
diff --git a/lit-test/compiler/irgen/eval.py b/lit-test/compiler/irgen/eval.py
deleted file mode 100644
index cd88b9b1e..000000000
--- a/lit-test/compiler/irgen/eval.py
+++ /dev/null
@@ -1,9 +0,0 @@
-# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
-# RUN: OutputCheck %s --file-to-check=%t
-
-2 + 2
-# CHECK-L: NoneType input.__modinit__() {
-# CHECK-L: 1:
-# CHECK-L:   %2 = int(width=32) eval `2 + 2`
-# CHECK-L:   return NoneType None
-# CHECK-L: }
diff --git a/lit-test/compiler/irgen/if.py b/lit-test/compiler/irgen/if.py
deleted file mode 100644
index 28d25d944..000000000
--- a/lit-test/compiler/irgen/if.py
+++ /dev/null
@@ -1,21 +0,0 @@
-# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
-# RUN: OutputCheck %s --file-to-check=%t
-
-if 1:
-    2
-else:
-    3
-
-# CHECK-L: NoneType input.__modinit__() {
-# CHECK-L: 1:
-# CHECK-L:   %2 = int(width=32) eval `1`
-# CHECK-L:   branch_if int(width=32) %2, ssa.basic_block %3, ssa.basic_block %5
-# CHECK-L: 3:
-# CHECK-L:   %4 = int(width=32) eval `2`
-# CHECK-L:   branch ssa.basic_block %7
-# CHECK-L: 5:
-# CHECK-L:   %6 = int(width=32) eval `3`
-# CHECK-L:   branch ssa.basic_block %7
-# CHECK-L: 7:
-# CHECK-L:   return NoneType None
-# CHECK-L: }
diff --git a/lit-test/compiler/irgen/while.py b/lit-test/compiler/irgen/while.py
deleted file mode 100644
index 6ec344be0..000000000
--- a/lit-test/compiler/irgen/while.py
+++ /dev/null
@@ -1,25 +0,0 @@
-# RUN: %python -m artiq.compiler.testbench.irgen %s >%t
-# RUN: OutputCheck %s --file-to-check=%t
-
-while 1:
-    2
-else:
-    3
-4
-
-# CHECK-L: NoneType input.__modinit__() {
-# CHECK-L: 1:
-# CHECK-L:   branch ssa.basic_block %2
-# CHECK-L: 2:
-# CHECK-L:   %9 = int(width=32) eval `1`
-# CHECK-L:   branch_if int(width=32) %9, ssa.basic_block %5, ssa.basic_block %7
-# CHECK-L: 4:
-# CHECK-L:   branch ssa.basic_block %7
-# CHECK-L: 5:
-# CHECK-L:   %6 = int(width=32) eval `2`
-# CHECK-L:   branch ssa.basic_block %7
-# CHECK-L: 7:
-# CHECK-L:   %8 = int(width=32) eval `3`
-# CHECK-L:   %13 = int(width=32) eval `4`
-# CHECK-L:   return NoneType None
-# CHECK-L: }