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sawg: add 1 coarse RTIO cycle between spline resets 

This keeps all events in the same SED lane and limits the number of SED lanes required.

Closes #1038
This commit is contained in:
Sebastien Bourdeauducq 2018-06-01 15:15:24 +08:00
parent 22506e849f
commit f5d55c6902
1 changed files with 10 additions and 1 deletions
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11
artiq/coredevice/sawg.py
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@ -342,7 +342,7 @@ class SAWG:
settings.
This method advances the timeline by the time required to perform all
seven writes to the configuration channel.
7 writes to the configuration channel, plus 9 coarse RTIO cycles.
"""
self.config.set_div(0, 0)
self.config.set_clr(1, 1, 1)
@ -352,11 +352,20 @@ class SAWG:
self.config.set_out_min(-1.)
self.config.set_out_max(1.)
self.frequency0.set_mu(0)
delay_mu(self.core.ref_multiplier)
self.frequency1.set_mu(0)
delay_mu(self.core.ref_multiplier)
self.frequency2.set_mu(0)
delay_mu(self.core.ref_multiplier)
self.phase0.set_mu(0)
delay_mu(self.core.ref_multiplier)
self.phase1.set_mu(0)
delay_mu(self.core.ref_multiplier)
self.phase2.set_mu(0)
delay_mu(self.core.ref_multiplier)
self.amplitude1.set_mu(0)
delay_mu(self.core.ref_multiplier)
self.amplitude2.set_mu(0)
delay_mu(self.core.ref_multiplier)
self.offset.set_mu(0)
delay_mu(self.core.ref_multiplier)