From f5d55c69023a37a54300874563946d781fed0918 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 1 Jun 2018 15:15:24 +0800 Subject: [PATCH] sawg: add 1 coarse RTIO cycle between spline resets This keeps all events in the same SED lane and limits the number of SED lanes required. Closes #1038 --- artiq/coredevice/sawg.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/artiq/coredevice/sawg.py b/artiq/coredevice/sawg.py index cc071ffa0..e3ff38c03 100644 --- a/artiq/coredevice/sawg.py +++ b/artiq/coredevice/sawg.py @@ -342,7 +342,7 @@ class SAWG: settings. This method advances the timeline by the time required to perform all - seven writes to the configuration channel. + 7 writes to the configuration channel, plus 9 coarse RTIO cycles. """ self.config.set_div(0, 0) self.config.set_clr(1, 1, 1) @@ -352,11 +352,20 @@ class SAWG: self.config.set_out_min(-1.) self.config.set_out_max(1.) self.frequency0.set_mu(0) + delay_mu(self.core.ref_multiplier) self.frequency1.set_mu(0) + delay_mu(self.core.ref_multiplier) self.frequency2.set_mu(0) + delay_mu(self.core.ref_multiplier) self.phase0.set_mu(0) + delay_mu(self.core.ref_multiplier) self.phase1.set_mu(0) + delay_mu(self.core.ref_multiplier) self.phase2.set_mu(0) + delay_mu(self.core.ref_multiplier) self.amplitude1.set_mu(0) + delay_mu(self.core.ref_multiplier) self.amplitude2.set_mu(0) + delay_mu(self.core.ref_multiplier) self.offset.set_mu(0) + delay_mu(self.core.ref_multiplier)