forked from M-Labs/artiq
kc705_drtio_master: fix number of fine RTIO timestamp bits
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@ -54,7 +54,7 @@ class Master(MiniSoC, AMPSoC):
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phy = ttl_simple.Inout(platform.request(sma))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_core = rtio.Core(rtio_channels, 4)
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self.submodules.rtio_core = rtio.Core(rtio_channels, 2)
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self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri])
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self.submodules.rtio = rtio.KernelInitiator(self.cridec.master)
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