forked from M-Labs/artiq
rtio: move CRI write comment to more appropriate location
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@ -6,6 +6,11 @@ from migen.genlib.record import *
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from misoc.interconnect.csr import *
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# CRI write happens in 3 cycles:
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# 1. set timestamp and channel
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# 2. set other payload elements and issue write command
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# 3. check status
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commands = {
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"nop": 0,
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@ -7,11 +7,6 @@ from artiq.gateware.rtio.sed import layouts
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__all__ = ["LaneDistributor"]
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# CRI write happens in 3 cycles:
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# 1. set timestamp and channel
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# 2. set other payload elements and issue write command
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# 3. check status
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class LaneDistributor(Module):
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def __init__(self, lane_count, seqn_width, layout_payload,
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compensation, glbl_fine_ts_width,
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